SRAM_CTRL/MAIN Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: 35f91f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.608m	8.761ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.080s	21.712us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.090s	18.633us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.560s	123.028us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.100s	79.781us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.850s	368.490us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.090s	18.633us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	79.781us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.439m	86.209ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.985m	24.079ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	19.390m	52.130ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.051m	23.062ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	40.651m	366.898ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	25.206m	20.680ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.671m	151.162ms	50	50	100.00
V2	executable	sram_ctrl_executable	21.918m	12.160ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.623m	1.377ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.629m	8.594ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.716m	3.816ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.648m	3.267ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.813m	3.657ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.454m	20.233ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.330s	2.405ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.057h	331.577ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.080s	38.531us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.700s	942.906us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.700s	942.906us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.080s	21.712us	5	5	100.00
		sram_ctrl_csr_rw	1.090s	18.633us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	79.781us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	29.668us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.080s	21.712us	5	5	100.00
		sram_ctrl_csr_rw	1.090s	18.633us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	79.781us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	29.668us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.135m	46.970ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.960s	3.174us	0	5	0.00
		sram_ctrl_tl_intg_err	4.750s	4.176ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.960s	3.174us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.750s	4.176ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.454m	20.233ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.454m	20.233ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.090s	18.633us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.918m	12.160ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.918m	12.160ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.918m	12.160ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.671m	151.162ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	9.660s	5.116ms	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.135m	46.970ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	8.510s	2.463ms	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.608m	8.761ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.608m	8.761ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.918m	12.160ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.960s	3.174us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.671m	151.162ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.960s	3.174us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.960s	3.174us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.608m	8.761ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.960s	3.174us	0	5	0.00
V2S		TOTAL			125	145	86.21
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.702m	6.762ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1170	1190	98.32

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 11 failures:
  • Test sram_ctrl_readback_err has 11 failures.

    • 2.sram_ctrl_readback_err.40792123390164959740861143278447792857353917917096285636378219762559566501259
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 674457033 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x41) != exp (0x4e)
        UVM_INFO @ 674457033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_readback_err.39766646634892971518512563822957960674367889411831987100582404979248419675573
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 666073780 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1c) != exp (0x31)
        UVM_INFO @ 666073780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 1.sram_ctrl_sec_cm.67651678579804981908635050328275444473848047298835741611194188436523429305011
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4765775 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4765775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.100306306917229397032824088837045339153092888477610756472602845696623672225938
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3935184 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3935184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending 'reqfifo_rvalid' has 4 failures:
  • Test sram_ctrl_mubi_enc_err has 4 failures.

    • 7.sram_ctrl_mubi_enc_err.11522944404852716366857590781368968736763926755111681795733431087952482186176
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 690267923 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 690267923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.sram_ctrl_mubi_enc_err.23162533588035053764977428465549967421252959425988071167695458318762280467895
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2634291971 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2634291971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.59214382872528171127736503468110046294499331194660715241258458507255823630727
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3173969 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3173969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---