SRAM_CTRL/RET Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: 35f91f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.804m	1.252ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.990s	13.454us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.020s	72.873us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.490s	1.210ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.040s	32.288us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.770s	49.254us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.020s	72.873us	20	20	100.00
		sram_ctrl_csr_aliasing	1.040s	32.288us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.250s	2.412ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.720s	191.489us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	21.417m	21.715ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.933m	4.934ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.443m	3.611ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	26.972m	17.697ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.300s	3.203ms	50	50	100.00
V2	executable	sram_ctrl_executable	21.898m	78.913ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.549m	2.636ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.585m	47.956ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.634m	532.222us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.803m	407.773us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.821m	430.425us	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.386m	18.478ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.190s	178.876us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.062h	60.668ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.070s	78.506us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.950s	430.143us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.950s	430.143us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.990s	13.454us	5	5	100.00
		sram_ctrl_csr_rw	1.020s	72.873us	20	20	100.00
		sram_ctrl_csr_aliasing	1.040s	32.288us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.130s	22.175us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.990s	13.454us	5	5	100.00
		sram_ctrl_csr_rw	1.020s	72.873us	20	20	100.00
		sram_ctrl_csr_aliasing	1.040s	32.288us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.130s	22.175us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	6.250s	7.812ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.070s	9.542us	0	5	0.00
		sram_ctrl_tl_intg_err	3.270s	379.625us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.070s	9.542us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.270s	379.625us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.386m	18.478ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.386m	18.478ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.020s	72.873us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.898m	78.913ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.898m	78.913ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.898m	78.913ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.300s	3.203ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.660s	202.116us	42	50	84.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	6.250s	7.812ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.720s	398.152us	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.804m	1.252ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.804m	1.252ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.898m	78.913ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.070s	9.542us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.300s	3.203ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.070s	9.542us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.070s	9.542us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.804m	1.252ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.070s	9.542us	0	5	0.00
V2S		TOTAL			122	145	84.14
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.833m	2.853ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1166	1190	97.98

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 10 failures:

  • Test sram_ctrl_readback_err has 10 failures.

    • 3.sram_ctrl_readback_err.109571209488859145057641574666055086296656935740242180196628619798530741985382
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  24185656 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x73) != exp (0x4b)
        UVM_INFO @  24185656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.sram_ctrl_readback_err.106207058595771939054843472109572071682851033880227046015252318238313618007749
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  23259671 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x51) != exp (0x34)
        UVM_INFO @  23259671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending 'reqfifo_rvalid' has 8 failures:

  • Test sram_ctrl_mubi_enc_err has 8 failures.

    • 5.sram_ctrl_mubi_enc_err.43443218173806254302244558679941582502744222560954299222156216312139511918488
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 109631002 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 109631002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_mubi_enc_err.29756194020201341919312039258429872287848023931230728209979096395786568374695
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 164910897 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 164910897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• Offending '(!$isunknown(rdata_o))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.3397198716475958926156148869136341786621755008585359072291200008001182365097
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   9542342 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   9542342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.38251866122082406207504480515526571086209353068529006860116147698241978728701
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1896989 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1896989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.24746237205356061235847573626961677832902654459969863508086040018460185872514
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @  19467836 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @  19467836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.60801791953437159410786602294434112585140511939993063886851097451487243284662
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4254869ps failed at 4254869ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4293331ps failed at 4293331ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.6090422722987261910210415316608499564502206096114719592811778696497114669225
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9689140 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9689140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1142) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 13.sram_ctrl_stress_all_with_rand_reset.21826875150326934431198655700958719423040414188902243182861172382715215812160
      Line 138, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3401778006 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3401778006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---