ADC_CTRL Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: `1f7db17`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	20.710s	6037.845us	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.950s	938.349us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.230s	443.289us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	119.520s	37736.726us	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.570s	1138.958us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.760s	537.589us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.230s	443.289us	20	20	100.00
		adc_ctrl_csr_aliasing	6.570s	1138.958us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	1403.910s	496961.548us	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1318.040s	491507.474us	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	1090.800s	492022.586us	49	50	98.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1105.590s	490480.374us	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	1595.350s	582988.598us	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1746.770s	611679.137us	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	1290.150s	507572.041us	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	1048.520s	381313.654us	37	50	74.00
V2	poweron_counter	adc_ctrl_poweron_counter	17.200s	4758.033us	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	130.560s	40272.102us	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	413.490s	131363.091us	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	2485.510s	1358949.577us	49	50	98.00
V2	alert_test	adc_ctrl_alert_test	2.660s	519.079us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.370s	386.539us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.310s	561.096us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.310s	561.096us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.950s	938.349us	5	5	100.00
		adc_ctrl_csr_rw	2.230s	443.289us	20	20	100.00
		adc_ctrl_csr_aliasing	6.570s	1138.958us	5	5	100.00
		adc_ctrl_same_csr_outstanding	11.270s	4477.972us	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.950s	938.349us	5	5	100.00
		adc_ctrl_csr_rw	2.230s	443.289us	20	20	100.00
		adc_ctrl_csr_aliasing	6.570s	1138.958us	5	5	100.00
		adc_ctrl_same_csr_outstanding	11.270s	4477.972us	20	20	100.00
V2		TOTAL			723	740	97.70
V2S	tl_intg_err	adc_ctrl_sec_cm	20.330s	7931.128us	5	5	100.00
		adc_ctrl_tl_intg_err	26.360s	8234.414us	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	26.360s	8234.414us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	804.650s	10000000.000us	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			900	920	97.83

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.35	99.05	96.03	100.00	100.00	98.64	95.95	91.76

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 10 failures:
- Test adc_ctrl_clock_gating has 7 failures.
  - 1.adc_ctrl_clock_gating.39633497287972135349219636110233541923123274620413471376026317050342472337581
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.adc_ctrl_clock_gating.113880061295601175337520688747558350739589160550821550310928891644040986373026
    Line 182, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
- Test adc_ctrl_filters_both has 1 failures.
  - 25.adc_ctrl_filters_both.93516350606993906069978645549735598921568655745211579513554658346301059239677
    Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all has 1 failures.
  - 29.adc_ctrl_stress_all.30253563797654638589152099037147422537847199846958343954501653161212870252054
    Line 251, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 38.adc_ctrl_stress_all_with_rand_reset.12019967216739293287906465690664717943114063572245015581273381854933802097232
    Line 195, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 5 failures:
- Test adc_ctrl_clock_gating has 4 failures.
  - 20.adc_ctrl_clock_gating.39584951177716130790598641951651119407197077562754972905609521264390118942281
    Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 199908682717 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 199908682717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.adc_ctrl_clock_gating.5163084822224728254372632333258217413333103168157585575609287210390450316758
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 2176172414 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 2176172414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 27.adc_ctrl_stress_all_with_rand_reset.30392132097267517844094645883588599574248822611831119518514007341446868627074
    Line 202, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 153040789829 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 153040789829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 4 failures:

Test adc_ctrl_filters_both has 1 failures.

5.adc_ctrl_filters_both.99807103558583233608635580917597551284415044676474861723839324054854644760978
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 173371935233 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 173371935233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_clock_gating has 2 failures.

27.adc_ctrl_clock_gating.88956434544777786450718485568196881018328594584472112312204176009800784336821
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 99624420239 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 99624420239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.adc_ctrl_clock_gating.105718535661551997449938173642778602539175202493598670567689672011574888209320
Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 251839790311 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 251839790311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_interrupt has 1 failures.

41.adc_ctrl_filters_interrupt.60692360068558141712553197692855776720020482141678407143869793203449851289672
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 163453052304 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 163453052304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(np_sample_cnt_q == '0)' has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 2.adc_ctrl_stress_all_with_rand_reset.161053980083616039954275265640364668272617210904489407620207408385773985035
    Line 214, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 2073515680 ps: (adc_ctrl_fsm.sv:386) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 2073515680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```