AES/MASKED Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: `1f7db17`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	61.584us	2	2	100.00
V1	smoke	aes_smoke	4.000s	106.459us	100	100	100.00
V1	csr_hw_reset	aes_csr_hw_reset	32.000s	62.412us	10	10	100.00
V1	csr_rw	aes_csr_rw	32.000s	166.839us	40	40	100.00
V1	csr_bit_bash	aes_csr_bit_bash	34.000s	341.257us	10	10	100.00
V1	csr_aliasing	aes_csr_aliasing	33.000s	240.589us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	32.000s	87.963us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	32.000s	166.839us	40	40	100.00
		aes_csr_aliasing	33.000s	240.589us	10	10	100.00
V1		TOTAL			212	212	100.00
V2	algorithm	aes_smoke	4.000s	106.459us	100	100	100.00
		aes_config_error	16.000s	796.785us	100	100	100.00
		aes_stress	99.000s	4719.950us	100	100	100.00
V2	key_length	aes_smoke	4.000s	106.459us	100	100	100.00
		aes_config_error	16.000s	796.785us	100	100	100.00
		aes_stress	99.000s	4719.950us	100	100	100.00
V2	back2back	aes_stress	99.000s	4719.950us	100	100	100.00
		aes_b2b	61.000s	1187.237us	100	100	100.00
V2	backpressure	aes_stress	99.000s	4719.950us	100	100	100.00
V2	multi_message	aes_smoke	4.000s	106.459us	100	100	100.00
		aes_config_error	16.000s	796.785us	100	100	100.00
		aes_stress	99.000s	4719.950us	100	100	100.00
		aes_alert_reset	9.000s	390.001us	98	100	98.00
V2	failure_test	aes_man_cfg_err	6.000s	454.469us	100	100	100.00
		aes_config_error	16.000s	796.785us	100	100	100.00
		aes_alert_reset	9.000s	390.001us	98	100	98.00
V2	trigger_clear_test	aes_clear	17.000s	718.423us	99	100	99.00
V2	nist_test_vectors	aes_nist_vectors	29.000s	4154.607us	2	2	100.00
V2	reset_recovery	aes_alert_reset	9.000s	390.001us	98	100	98.00
V2	stress	aes_stress	99.000s	4719.950us	100	100	100.00
V2	sideload	aes_stress	99.000s	4719.950us	100	100	100.00
		aes_sideload	30.000s	4304.661us	100	100	100.00
V2	deinitialization	aes_deinit	8.000s	307.952us	100	100	100.00
V2	stress_all	aes_stress_all	328.000s	12703.475us	20	20	100.00
V2	alert_test	aes_alert_test	3.000s	71.309us	100	100	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	33.000s	573.146us	40	40	100.00
V2	tl_d_illegal_access	aes_tl_errors	33.000s	573.146us	40	40	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	32.000s	62.412us	10	10	100.00
		aes_csr_rw	32.000s	166.839us	40	40	100.00
		aes_csr_aliasing	33.000s	240.589us	10	10	100.00
		aes_same_csr_outstanding	32.000s	59.155us	40	40	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	32.000s	62.412us	10	10	100.00
		aes_csr_rw	32.000s	166.839us	40	40	100.00
		aes_csr_aliasing	33.000s	240.589us	10	10	100.00
		aes_same_csr_outstanding	32.000s	59.155us	40	40	100.00
V2		TOTAL			999	1002	99.70
V2S	reseeding	aes_reseed	27.000s	1567.652us	100	100	100.00
V2S	fault_inject	aes_fi	9.000s	499.782us	100	100	100.00
		aes_control_fi	59.000s	200000.000us	548	600	91.33
		aes_cipher_fi	57.000s	10034.510us	670	700	95.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	32.000s	116.994us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	32.000s	116.994us	40	40	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	32.000s	116.994us	40	40	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	32.000s	116.994us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	33.000s	243.072us	40	40	100.00
V2S	tl_intg_err	aes_tl_intg_err	33.000s	830.558us	40	40	100.00
		aes_sec_cm	10.000s	1928.363us	10	10	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	33.000s	830.558us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	390.001us	98	100	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	32.000s	116.994us	40	40	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	106.459us	100	100	100.00
		aes_stress	99.000s	4719.950us	100	100	100.00
		aes_alert_reset	9.000s	390.001us	98	100	98.00
		aes_core_fi	31.000s	10006.314us	137	140	97.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	32.000s	116.994us	40	40	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	108.654us	100	100	100.00
		aes_stress	99.000s	4719.950us	100	100	100.00
V2S	sec_cm_key_sideload	aes_stress	99.000s	4719.950us	100	100	100.00
		aes_sideload	30.000s	4304.661us	100	100	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	108.654us	100	100	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	108.654us	100	100	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	108.654us	100	100	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	108.654us	100	100	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	108.654us	100	100	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	99.000s	4719.950us	100	100	100.00
V2S	sec_cm_key_masking	aes_stress	99.000s	4719.950us	100	100	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	499.782us	100	100	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	499.782us	100	100	100.00
		aes_control_fi	59.000s	200000.000us	548	600	91.33
		aes_cipher_fi	57.000s	10034.510us	670	700	95.71
		aes_ctr_fi	19.000s	10034.716us	99	100	99.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	499.782us	100	100	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	499.782us	100	100	100.00
		aes_control_fi	59.000s	200000.000us	548	600	91.33
		aes_cipher_fi	57.000s	10034.510us	670	700	95.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	57.000s	10034.510us	670	700	95.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	499.782us	100	100	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	499.782us	100	100	100.00
		aes_control_fi	59.000s	200000.000us	548	600	91.33
		aes_ctr_fi	19.000s	10034.716us	99	100	99.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	499.782us	100	100	100.00
		aes_control_fi	59.000s	200000.000us	548	600	91.33
		aes_cipher_fi	57.000s	10034.510us	670	700	95.71
		aes_ctr_fi	19.000s	10034.716us	99	100	99.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	390.001us	98	100	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	499.782us	100	100	100.00
		aes_control_fi	59.000s	200000.000us	548	600	91.33
		aes_cipher_fi	57.000s	10034.510us	670	700	95.71
		aes_ctr_fi	19.000s	10034.716us	99	100	99.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	499.782us	100	100	100.00
		aes_control_fi	59.000s	200000.000us	548	600	91.33
		aes_cipher_fi	57.000s	10034.510us	670	700	95.71
		aes_ctr_fi	19.000s	10034.716us	99	100	99.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	499.782us	100	100	100.00
		aes_control_fi	59.000s	200000.000us	548	600	91.33
		aes_ctr_fi	19.000s	10034.716us	99	100	99.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	499.782us	100	100	100.00
		aes_control_fi	59.000s	200000.000us	548	600	91.33
		aes_cipher_fi	57.000s	10034.510us	670	700	95.71
V2S		TOTAL			1884	1970	95.63
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	59.000s	13466.741us	0	20	0.00
V3		TOTAL			0	20	0.00
		TOTAL			3095	3204	96.60

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.39	98.64	96.54	99.45	95.46	97.99	100.00	98.36	98.79

Failure Buckets

Job timed out after * minutes has 40 failures:
- Test aes_control_fi has 29 failures.
  - 14.aes_control_fi.11339865073852008960444351688842790000291186987830041039584486732696357803320
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 20.aes_control_fi.80396351931472234054430576428875179461699695041578154314403796122369128339384
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 27 more failures.
- Test aes_cipher_fi has 11 failures.
  - 102.aes_cipher_fi.64567204165290019391998797280671715464285264319844817231042905504905876800949
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/102.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 117.aes_cipher_fi.16184406557087780343177484069626213015493815152252063970481307614590713382358
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/117.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 22 failures:
- Test aes_control_fi has 22 failures.
  - 35.aes_control_fi.98136999256188437733818487011855495587212798449611278343334402752276579256766
    Line 149, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003838347 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003838347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 50.aes_control_fi.89598374239708076515386475691450542999019299930621685149150628129491681386537
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/50.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004033188 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004033188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 19 failures:
- Test aes_cipher_fi has 19 failures.
  - 27.aes_cipher_fi.73676541449617222817214682206985358563712018334701274232855532617393942337327
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002642983 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002642983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 72.aes_cipher_fi.6656082150872019820707731112195362251363775443139265493513226408617562168107
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/72.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003977545 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003977545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 14 failures:

Test aes_stress_all_with_rand_reset has 14 failures.

0.aes_stress_all_with_rand_reset.16319488859755938391522793804677826473997511268760545121013394190890053476065
Line 281, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1329266091 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1329266091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.13892012229829500247279529691066403345620985285681590682891627056707405732938
Line 1125, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 728008745 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 728008745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 6.aes_stress_all_with_rand_reset.11607376302585679724491092600215935966339884012125044366618497973828528143348
    Line 657, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13466740526 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13466740526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.aes_stress_all_with_rand_reset.103027466105005302760135512664243558443379442663076045580606566602629374197016
    Line 170, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1963471987 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1963471987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 20.aes_core_fi.58975130986233398041983300240522130170845851524721323549842149633167426629590
    Line 145, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10024129506 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024129506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 21.aes_core_fi.28239770660661365137418495739312845103520254739808040288775189432995677101466
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/21.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013606711 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013606711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.96133426362574759538517144705122507171127500972340247091265922575794691477930
    Line 161, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  20026962 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  20026962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.aes_stress_all_with_rand_reset.75419339702776962312452736166591177438669181997738410108126257725569427467897
    Line 420, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1469380197 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1469380197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.2513285932346840909727374586774075646215445482856137986670544026381413354358
    Line 574, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 365208415 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 365208415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

7.aes_alert_reset.48615770831340933631369050998910106605183873619541594895596890115162395432023
Line 3906, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 41316353 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 41276353 PS)
  UVM_ERROR @  41316353 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  41316353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 45.aes_clear.19942665300731058913060543707790065599816250773653735513081774189723861196998
    Line 2295, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/45.aes_clear/latest/run.log
```
  UVM_FATAL @ 100442717 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
           TEST FAILED MESSAGES DID NOT MATCH

                 0 85 	 78 	 a0 	 0
                 1 a0 	 00 	 5e 	 0
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 247.aes_control_fi.64475882125504494223331115436384404520477176160885652202240588153721671163013
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/247.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

29.aes_alert_reset.109412060717507746772133561692771708358077378005256339607157057275054266659921
Line 4322, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/29.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 41670288 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 41630288 PS)
  UVM_ERROR @  41670288 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  41670288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_ctr_fi_vseq.sv:59) [aes_ctr_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_ctr_fi has 1 failures.
  - 49.aes_ctr_fi.73173600996338214281089317421580774727723421734335528490205419335042344862647
    Line 139, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/49.aes_ctr_fi/latest/run.log
```
  UVM_FATAL @ 10034715681 ps: (aes_ctr_fi_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.aes_ctr_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10034715681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```