CSRNG Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 5.000s 251.902us 50 50 100.00
V1 csr_hw_reset csrng_csr_hw_reset 4.000s 304.617us 5 5 100.00
V1 csr_rw csrng_csr_rw 3.000s 33.953us 20 20 100.00
V1 csr_bit_bash csrng_csr_bit_bash 33.000s 2161.864us 5 5 100.00
V1 csr_aliasing csrng_csr_aliasing 5.000s 227.513us 5 5 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 4.000s 312.497us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 3.000s 33.953us 20 20 100.00
csrng_csr_aliasing 5.000s 227.513us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 interrupts csrng_intr 15.000s 949.513us 200 200 100.00
V2 alerts csrng_alert 53.000s 4492.797us 500 500 100.00
V2 err csrng_err 4.000s 118.789us 500 500 100.00
V2 cmds csrng_cmds 607.000s 60183.537us 50 50 100.00
V2 life cycle csrng_cmds 607.000s 60183.537us 50 50 100.00
V2 stress_all csrng_stress_all 1288.000s 91922.481us 50 50 100.00
V2 intr_test csrng_intr_test 4.000s 247.662us 50 50 100.00
V2 alert_test csrng_alert_test 4.000s 221.195us 50 50 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 18.000s 1704.764us 20 20 100.00
V2 tl_d_illegal_access csrng_tl_errors 18.000s 1704.764us 20 20 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 4.000s 304.617us 5 5 100.00
csrng_csr_rw 3.000s 33.953us 20 20 100.00
csrng_csr_aliasing 5.000s 227.513us 5 5 100.00
csrng_same_csr_outstanding 5.000s 95.634us 20 20 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 4.000s 304.617us 5 5 100.00
csrng_csr_rw 3.000s 33.953us 20 20 100.00
csrng_csr_aliasing 5.000s 227.513us 5 5 100.00
csrng_same_csr_outstanding 5.000s 95.634us 20 20 100.00
V2 TOTAL 1440 1440 100.00
V2S tl_intg_err csrng_tl_intg_err 12.000s 541.679us 20 20 100.00
csrng_sec_cm 7.000s 180.062us 5 5 100.00
V2S sec_cm_config_regwen csrng_csr_rw 3.000s 33.953us 20 20 100.00
csrng_regwen 4.000s 137.642us 50 50 100.00
V2S sec_cm_config_mubi csrng_alert 53.000s 4492.797us 500 500 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 1288.000s 91922.481us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
csrng_sec_cm 7.000s 180.062us 5 5 100.00
V2S sec_cm_updrsp_fsm_sparse csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
csrng_sec_cm 7.000s 180.062us 5 5 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
csrng_sec_cm 7.000s 180.062us 5 5 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
csrng_sec_cm 7.000s 180.062us 5 5 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
csrng_sec_cm 7.000s 180.062us 5 5 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
csrng_sec_cm 7.000s 180.062us 5 5 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
csrng_sec_cm 7.000s 180.062us 5 5 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
csrng_sec_cm 7.000s 180.062us 5 5 100.00
V2S sec_cm_ctrl_mubi csrng_alert 53.000s 4492.797us 500 500 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
V2S sec_cm_constants_lc_gated csrng_stress_all 1288.000s 91922.481us 50 50 100.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 53.000s 4492.797us 500 500 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 12.000s 541.679us 20 20 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
csrng_sec_cm 7.000s 180.062us 5 5 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
csrng_sec_cm 7.000s 180.062us 5 5 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 15.000s 949.513us 200 200 100.00
csrng_err 4.000s 118.789us 500 500 100.00
V2S TOTAL 75 75 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 291.000s 7616.266us 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 1630 1630 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.53 98.78 97.04 99.78 96.69 92.08 97.62 95.40 90.00