EDN Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.360s	25.481us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.870s	47.864us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.990s	17.635us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.440s	979.255us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.260s	135.674us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.650s	109.661us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.990s	17.635us	20	20	100.00
		edn_csr_aliasing	1.260s	135.674us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	125.110s	10324.919us	300	300	100.00
V2	csrng_commands	edn_genbits	125.110s	10324.919us	300	300	100.00
V2	genbits	edn_genbits	125.110s	10324.919us	300	300	100.00
V2	interrupts	edn_intr	1.450s	21.073us	50	50	100.00
V2	alerts	edn_alert	1.740s	33.902us	200	200	100.00
V2	errs	edn_err	1.690s	47.055us	100	100	100.00
V2	disable	edn_disable	1.280s	13.610us	50	50	100.00
		edn_disable_auto_req_mode	1.830s	47.227us	50	50	100.00
V2	stress_all	edn_stress_all	5.580s	970.154us	50	50	100.00
V2	intr_test	edn_intr_test	1.070s	14.910us	50	50	100.00
V2	alert_test	edn_alert_test	1.520s	48.544us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.850s	225.018us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.850s	225.018us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.870s	47.864us	5	5	100.00
		edn_csr_rw	0.990s	17.635us	20	20	100.00
		edn_csr_aliasing	1.260s	135.674us	5	5	100.00
		edn_same_csr_outstanding	1.230s	76.079us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.870s	47.864us	5	5	100.00
		edn_csr_rw	0.990s	17.635us	20	20	100.00
		edn_csr_aliasing	1.260s	135.674us	5	5	100.00
		edn_same_csr_outstanding	1.230s	76.079us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	5.810s	920.284us	5	5	100.00
		edn_tl_intg_err	3.380s	487.117us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.260s	18.153us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.740s	33.902us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.810s	920.284us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.810s	920.284us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.810s	920.284us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.810s	920.284us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.740s	33.902us	200	200	100.00
		edn_sec_cm	5.810s	920.284us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.740s	33.902us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.380s	487.117us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	8781.990s	10000000.000us	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			1116	1130	98.76

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	98.87	94.29	97.02	92.44	96.33	97.56	92.94

Failure Buckets

• Job timed out after * minutes has 13 failures:
  • Test edn_stress_all_with_rand_reset has 13 failures.

    • 0.edn_stress_all_with_rand_reset.82309557653932166637924005579781761164269174421802693647117754674349153779472
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 6.edn_stress_all_with_rand_reset.29352507417687416093018213760792907280132480349546193405927035910359485416558
      Log /nightly/current_run/scratch/master/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 11 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 30.edn_stress_all_with_rand_reset.68423228559710125228871176377967377482892858634233448371374371237636217439072
      Line 456, in log /nightly/current_run/scratch/master/edn-sim-vcs/30.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---