HMAC Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.600s	306.544us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.330s	33.685us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.300s	27.997us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.580s	308.885us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	5.420s	107.607us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	1646.810s	136574.128us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.300s	27.997us	20	20	100.00
		hmac_csr_aliasing	5.420s	107.607us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	98.970s	1969.724us	10	10	100.00
V2	back_pressure	hmac_back_pressure	96.410s	1487.547us	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	255.530s	58086.642us	30	30	100.00
		hmac_test_sha384_vectors	572.340s	30399.554us	75	75	100.00
		hmac_test_sha512_vectors	602.050s	14761.744us	75	75	100.00
		hmac_test_hmac256_vectors	15.380s	370.121us	50	50	100.00
		hmac_test_hmac384_vectors	16.760s	406.869us	60	60	100.00
		hmac_test_hmac512_vectors	18.630s	516.748us	75	75	100.00
V2	burst_wr	hmac_burst_wr	32.420s	5982.338us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	1133.910s	13328.622us	10	10	100.00
V2	error	hmac_error	108.170s	57235.255us	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	83.960s	9744.623us	10	10	100.00
V2	save_and_restore	hmac_smoke	13.600s	306.544us	10	10	100.00
		hmac_long_msg	98.970s	1969.724us	10	10	100.00
		hmac_back_pressure	96.410s	1487.547us	25	25	100.00
		hmac_datapath_stress	1133.910s	13328.622us	10	10	100.00
		hmac_burst_wr	32.420s	5982.338us	50	50	100.00
		hmac_stress_all	1694.720s	24011.340us	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	13.600s	306.544us	10	10	100.00
		hmac_long_msg	98.970s	1969.724us	10	10	100.00
		hmac_back_pressure	96.410s	1487.547us	25	25	100.00
		hmac_datapath_stress	1133.910s	13328.622us	10	10	100.00
		hmac_wipe_secret	83.960s	9744.623us	10	10	100.00
		hmac_test_sha256_vectors	255.530s	58086.642us	30	30	100.00
		hmac_test_sha384_vectors	572.340s	30399.554us	75	75	100.00
		hmac_test_sha512_vectors	602.050s	14761.744us	75	75	100.00
		hmac_test_hmac256_vectors	15.380s	370.121us	50	50	100.00
		hmac_test_hmac384_vectors	16.760s	406.869us	60	60	100.00
		hmac_test_hmac512_vectors	18.630s	516.748us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	13.600s	306.544us	10	10	100.00
		hmac_long_msg	98.970s	1969.724us	10	10	100.00
		hmac_back_pressure	96.410s	1487.547us	25	25	100.00
		hmac_datapath_stress	1133.910s	13328.622us	10	10	100.00
		hmac_burst_wr	32.420s	5982.338us	50	50	100.00
		hmac_error	108.170s	57235.255us	10	10	100.00
		hmac_wipe_secret	83.960s	9744.623us	10	10	100.00
		hmac_test_sha256_vectors	255.530s	58086.642us	30	30	100.00
		hmac_test_sha384_vectors	572.340s	30399.554us	75	75	100.00
		hmac_test_sha512_vectors	602.050s	14761.744us	75	75	100.00
		hmac_test_hmac256_vectors	15.380s	370.121us	50	50	100.00
		hmac_test_hmac384_vectors	16.760s	406.869us	60	60	100.00
		hmac_test_hmac512_vectors	18.630s	516.748us	75	75	100.00
		hmac_stress_all	1694.720s	24011.340us	50	50	100.00
V2	stress_all	hmac_stress_all	1694.720s	24011.340us	50	50	100.00
V2	alert_test	hmac_alert_test	0.950s	27.121us	50	50	100.00
V2	intr_test	hmac_intr_test	0.960s	14.071us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.420s	426.810us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.420s	426.810us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.330s	33.685us	5	5	100.00
		hmac_csr_rw	1.300s	27.997us	20	20	100.00
		hmac_csr_aliasing	5.420s	107.607us	5	5	100.00
		hmac_same_csr_outstanding	2.770s	286.111us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.330s	33.685us	5	5	100.00
		hmac_csr_rw	1.300s	27.997us	20	20	100.00
		hmac_csr_aliasing	5.420s	107.607us	5	5	100.00
		hmac_same_csr_outstanding	2.770s	286.111us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.460s	367.611us	5	5	100.00
		hmac_tl_intg_err	4.620s	840.572us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.620s	840.572us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.600s	306.544us	10	10	100.00
V3	stress_reset	hmac_stress_reset	5.910s	208.223us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	470.150s	73150.820us	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	4.150s	2339.436us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.18	99.95	96.91	100.00	100.00	99.83	97.61	99.95