KEYMGR Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	27.160s	9594.983us	50	50	100.00
V1	random	keymgr_random	23.610s	7816.917us	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.280s	16.703us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.760s	29.322us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	14.620s	1314.197us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.050s	921.553us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.550s	75.562us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.760s	29.322us	20	20	100.00
		keymgr_csr_aliasing	8.050s	921.553us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	52.480s	7112.290us	49	50	98.00
V2	sideload	keymgr_sideload	23.810s	2052.584us	50	50	100.00
		keymgr_sideload_kmac	33.890s	1542.543us	50	50	100.00
		keymgr_sideload_aes	55.590s	7156.303us	50	50	100.00
		keymgr_sideload_otbn	39.540s	6061.504us	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	20.250s	3031.817us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	8.790s	251.497us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.510s	344.433us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	55.510s	5117.296us	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	56.850s	5108.895us	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	12.450s	662.858us	50	50	100.00
V2	stress_all	keymgr_stress_all	564.420s	79208.790us	49	50	98.00
V2	intr_test	keymgr_intr_test	1.270s	41.206us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.390s	21.687us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.440s	139.819us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.440s	139.819us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.280s	16.703us	5	5	100.00
		keymgr_csr_rw	1.760s	29.322us	20	20	100.00
		keymgr_csr_aliasing	8.050s	921.553us	5	5	100.00
		keymgr_same_csr_outstanding	3.750s	235.191us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.280s	16.703us	5	5	100.00
		keymgr_csr_rw	1.760s	29.322us	20	20	100.00
		keymgr_csr_aliasing	8.050s	921.553us	5	5	100.00
		keymgr_same_csr_outstanding	3.750s	235.191us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	tl_intg_err	keymgr_tl_intg_err	8.350s	517.434us	20	20	100.00
		keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.470s	630.870us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.470s	630.870us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.470s	630.870us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.470s	630.870us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.250s	598.720us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.350s	517.434us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.470s	630.870us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	52.480s	7112.290us	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_csr_rw	1.760s	29.322us	20	20	100.00
		keymgr_random	23.610s	7816.917us	50	50	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_csr_rw	1.760s	29.322us	20	20	100.00
		keymgr_random	23.610s	7816.917us	50	50	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_csr_rw	1.760s	29.322us	20	20	100.00
		keymgr_random	23.610s	7816.917us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.790s	251.497us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	56.850s	5108.895us	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	56.850s	5108.895us	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	23.610s	7816.917us	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	26.860s	3675.433us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	16.600s	1444.992us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.790s	251.497us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	16.600s	1444.992us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	16.600s	1444.992us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	16.600s	1444.992us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	21.140s	1017.198us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	16.600s	1444.992us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	21.880s	1984.221us	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1084	1110	97.66

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.68	99.13	98.15	98.51	100.00	99.01	97.72	91.23

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test keymgr_stress_all_with_rand_reset has 21 failures.

    • 0.keymgr_stress_all_with_rand_reset.36683025565808357780001983386438556859434446711567116837426937750076297588235
      Line 1069, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 798753372 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 798753372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.keymgr_stress_all_with_rand_reset.20626371957033981832695839941719379559323245556663462857819029444715256532903
      Line 542, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 924287107 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 924287107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:

  • Test keymgr_hwsw_invalid_input has 1 failures.

    • 17.keymgr_hwsw_invalid_input.18529032761198260115569000734025242295888169709948693441446613106103499051115
      Line 508, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest/run.log

        UVM_ERROR @ 129518425 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @ 129518425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 21.keymgr_stress_all_with_rand_reset.55361883209915091651795307572421382046923277465128610495382281531183339586631
      Line 404, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 191995227 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
        UVM_INFO @ 191995227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:

  • Test keymgr_lc_disable has 1 failures.

    • 27.keymgr_lc_disable.36756875228967642876235840053990273621549738602571132621613229910602308947322
      Line 470, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/27.keymgr_lc_disable/latest/run.log

        UVM_ERROR @ 122261216 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (5 [0x5] vs 6 [0x6])
        UVM_INFO @ 122261216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 37.keymgr_stress_all.53184117186638335863044782819611666182269191500257198977428677482172710491125
      Line 730, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/37.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 475539263 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_0
        UVM_INFO @ 475539263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:

  • Test keymgr_cfg_regwen has 1 failures.

    • 42.keymgr_cfg_regwen.9924149812554776684178811198341862894486073849344421955580208802908718731202
      Line 219, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @  28288874 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @  28288874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---