KMAC/UNMASKED Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	81.970s	19254.365us	100	100	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.640s	259.230us	10	10	100.00
V1	csr_rw	kmac_csr_rw	1.510s	32.039us	40	40	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.080s	4402.699us	10	10	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.920s	2070.900us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.190s	89.428us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.510s	32.039us	40	40	100.00
		kmac_csr_aliasing	8.920s	2070.900us	10	10	100.00
V1	mem_walk	kmac_mem_walk	1.100s	26.268us	10	10	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.980s	159.722us	10	10	100.00
V1		TOTAL			230	230	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	3508.640s	326126.876us	100	100	100.00
V2	burst_write	kmac_burst_write	1360.030s	28841.959us	100	100	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	2252.440s	63457.186us	10	10	100.00
		kmac_test_vectors_sha3_256	2235.620s	91750.261us	10	10	100.00
		kmac_test_vectors_sha3_384	1596.480s	67171.262us	10	10	100.00
		kmac_test_vectors_sha3_512	1232.290s	930050.003us	10	10	100.00
		kmac_test_vectors_shake_128	2656.740s	343021.187us	10	10	100.00
		kmac_test_vectors_shake_256	1900.210s	88982.129us	10	10	100.00
		kmac_test_vectors_kmac	3.550s	207.655us	10	10	100.00
		kmac_test_vectors_kmac_xof	4.150s	540.490us	10	10	100.00
V2	sideload	kmac_sideload	486.260s	21730.754us	100	100	100.00
V2	app	kmac_app	361.540s	34473.017us	100	100	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	349.290s	79226.603us	20	20	100.00
V2	entropy_refresh	kmac_entropy_refresh	369.610s	38975.476us	100	100	100.00
V2	error	kmac_error	477.180s	22526.907us	99	100	99.00
V2	key_error	kmac_key_error	17.360s	7803.750us	100	100	100.00
V2	sideload_invalid	kmac_sideload_invalid	156.890s	10091.695us	87	100	87.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.230s	26712.102us	40	40	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.540s	8747.455us	40	40	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	102.100s	32748.506us	20	20	100.00
V2	lc_escalation	kmac_lc_escalation	51.430s	1913.789us	100	100	100.00
V2	stress_all	kmac_stress_all	3073.260s	1426981.914us	99	100	99.00
V2	intr_test	kmac_intr_test	1.280s	30.993us	100	100	100.00
V2	alert_test	kmac_alert_test	1.280s	38.750us	100	100	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.130s	316.277us	40	40	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.130s	316.277us	40	40	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.640s	259.230us	10	10	100.00
		kmac_csr_rw	1.510s	32.039us	40	40	100.00
		kmac_csr_aliasing	8.920s	2070.900us	10	10	100.00
		kmac_same_csr_outstanding	3.460s	444.156us	40	40	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.640s	259.230us	10	10	100.00
		kmac_csr_rw	1.510s	32.039us	40	40	100.00
		kmac_csr_aliasing	8.920s	2070.900us	10	10	100.00
		kmac_same_csr_outstanding	3.460s	444.156us	40	40	100.00
V2		TOTAL			1465	1480	98.99
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.930s	636.769us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.930s	636.769us	40	40	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.930s	636.769us	40	40	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.930s	636.769us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.240s	290.845us	40	40	100.00
V2S	tl_intg_err	kmac_tl_intg_err	5.620s	485.059us	40	40	100.00
		kmac_sec_cm	89.920s	6070.068us	10	10	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.620s	485.059us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	51.430s	1913.789us	100	100	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	81.970s	19254.365us	100	100	100.00
V2S	sec_cm_key_sideload	kmac_sideload	486.260s	21730.754us	100	100	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.930s	636.769us	40	40	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	89.920s	6070.068us	10	10	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	89.920s	6070.068us	10	10	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	89.920s	6070.068us	10	10	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	81.970s	19254.365us	100	100	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	51.430s	1913.789us	100	100	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	89.920s	6070.068us	10	10	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	339.010s	135249.192us	20	20	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	81.970s	19254.365us	100	100	100.00
V2S		TOTAL			150	150	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	361.560s	5945.043us	15	20	75.00
V3		TOTAL			15	20	75.00
		TOTAL			1860	1880	98.94

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.68	97.69	94.48	100.00	73.55	96.04	97.74	96.26

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 4 failures:

  • Test kmac_sideload_invalid has 4 failures.

    • 25.kmac_sideload_invalid.15365580349604200091069099400811760529915776001756648438365950257718041361133
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10014246867 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf69ba000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10014246867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 26.kmac_sideload_invalid.55189413030981919053715132851780514650299669963977746092521382170592166642617
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10033375347 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x942ce000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10033375347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 3 failures:

  • Test kmac_stress_all_with_rand_reset has 3 failures.

    • 3.kmac_stress_all_with_rand_reset.47126055384917992946890764978368744549214192129313123018433438323833579648134
      Line 370, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21875009873 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 21875009873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.kmac_stress_all_with_rand_reset.39410854889785860564749495104042235814655631649944655598602015155181236124931
      Line 415, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5795387126 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 5795387126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 2.kmac_stress_all_with_rand_reset.25364473173568647838432132982076404485701472677711837501824201109978436505565
      Line 180, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14280298293 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14280298293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.kmac_stress_all_with_rand_reset.33008058755762999642729901526075341544258656213056628984900593610099005606885
      Line 143, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8913910432 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8913910432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 9.kmac_sideload_invalid.102528781737969739752834720842615433514238180331095433838927474001935862390140
      Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10219952855 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3fd3d000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10219952855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 14.kmac_sideload_invalid.62121600996536044340396784889719472839699513123903013914121831216890551353437
      Line 77, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10072191574 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x501ba000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10072191574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 16.kmac_sideload_invalid.39395502761813585435695705577999108239544580965431860755050189837975046024820
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10036954089 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd2916000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10036954089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 46.kmac_sideload_invalid.67287231056339324319064025113913876941942651734551144361032695942358754121900
      Line 80, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/46.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10182400603 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8f35e000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10182400603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 34.kmac_sideload_invalid.83424197897708193861905582430910085767284130325190670342206034999684463650805
      Line 83, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/34.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10251391533 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb375c000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
        UVM_INFO @ 10251391533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 44.kmac_sideload_invalid.87426828097713378503481021335266290841250495233263828572675243986662307115787
      Line 84, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10069011979 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x20a4c000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
        UVM_INFO @ 10069011979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.109130029327574156551070281337917379954993830909214607278643795628774199454298
      Line 87, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10114729015 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3fcb1000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
        UVM_INFO @ 10114729015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 13.kmac_sideload_invalid.36801598758236675097173666203585719426378982381606888726314021942279505484068
      Line 84, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/13.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10429879551 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x61e20000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
        UVM_INFO @ 10429879551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 42.kmac_sideload_invalid.114169847380121713831893835639164013491518313853102572923267772267317685896447
      Line 97, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10091695257 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbdd03000, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
        UVM_INFO @ 10091695257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_error has 1 failures.

    • 35.kmac_error.31718885943223210251568795944174569613641407834600286088766405815748328499283
      Line 224, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/35.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_stress_all has 1 failures.

    • 46.kmac_stress_all.617140990393403249568096788931802014756208430064161508936949649144890005976
      Line 83, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/46.kmac_stress_all/latest/run.log

        UVM_ERROR @ 612242227 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 612242227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---