1f7db17| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 9.000s | 271.063us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 41.000s | 232.260us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 9.000s | 40.633us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 8.000s | 77.837us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 11.000s | 36.755us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 8.000s | 13.056us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 13.000s | 25.032us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 8.000s | 77.837us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 8.000s | 13.056us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 41.000s | 365.111us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 26.000s | 128.486us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 47.000s | 303.045us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 45.000s | 1700.108us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 471.000s | 3386.501us | 9 | 10 | 90.00 |
| V2 | stress_all | otbn_stress_all | 87.000s | 345.674us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 17.000s | 53.001us | 57 | 60 | 95.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 28.564us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 36.000s | 144.497us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 6.000s | 21.390us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 9.000s | 12.278us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 13.000s | 140.400us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 13.000s | 140.400us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 9.000s | 40.633us | 5 | 5 | 100.00 |
| otbn_csr_rw | 8.000s | 77.837us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 8.000s | 13.056us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 9.000s | 21.964us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 9.000s | 40.633us | 5 | 5 | 100.00 |
| otbn_csr_rw | 8.000s | 77.837us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 8.000s | 13.056us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 9.000s | 21.964us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 242 | 246 | 98.37 | |||
| V2S | mem_integrity | otbn_imem_err | 10.000s | 20.480us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 39.979us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 13.000s | 251.874us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 12.000s | 74.997us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 11.000s | 130.069us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 7.000s | 18.992us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 7.000s | 16.640us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 6.000s | 12.409us | 2 | 2 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 8.000s | 16.815us | 8 | 10 | 80.00 |
| V2S | tl_intg_err | otbn_tl_intg_err | 41.000s | 200.260us | 20 | 20 | 100.00 |
| otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 55.000s | 311.622us | 19 | 20 | 95.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 |
| V2S | prim_count_check | otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 9.000s | 271.063us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 12.000s | 39.979us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 10.000s | 20.480us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 41.000s | 200.260us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 17.000s | 53.001us | 57 | 60 | 95.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 10.000s | 20.480us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 39.979us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 28.564us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 16.640us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 41.000s | 232.260us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 10.000s | 20.480us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 39.979us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 28.564us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 16.640us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 17.000s | 53.001us | 57 | 60 | 95.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 10.000s | 20.480us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 39.979us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 28.564us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 16.640us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 41.000s | 232.260us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 48.000s | 190.795us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 36.504us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 25.000s | 376.789us | 4 | 5 | 80.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 25.000s | 376.789us | 4 | 5 | 80.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 9.000s | 32.509us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 12.000s | 75.833us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 28.000s | 213.140us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 28.000s | 213.140us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 12.000s | 39.279us | 5 | 7 | 71.43 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 41.000s | 232.260us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 41.000s | 232.260us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 41.000s | 232.260us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 471.000s | 3386.501us | 9 | 10 | 90.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 41.000s | 232.260us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 41.000s | 232.260us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 12.000s | 22.995us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 41.000s | 232.260us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 257.000s | 1113.156us | 2 | 5 | 40.00 |
| V2S | TOTAL | 153 | 163 | 93.87 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 567.000s | 7225.487us | 1 | 10 | 10.00 |
| V3 | TOTAL | 1 | 10 | 10.00 | |||
| TOTAL | 562 | 585 | 96.07 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 99.05 | 99.58 | 95.02 | 99.68 | 93.18 | 93.89 | 100.00 | 96.38 | 100.00 |
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
0.otbn_stress_all_with_rand_reset.88372204775336615581823754472753106812572702820581835452974372242290697206417
Line 166, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 122301908 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 122301908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_stress_all_with_rand_reset.71015419986804003578418977418048334934765095721305789787304699304487338846687
Line 172, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 202753512 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 202753512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 3 failures:
1.otbn_sec_cm.14329901979771590249725117957977369307216876760961080886996749578936442786767
Line 117, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 172137258 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 172137258 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 172137258 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 172137258 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 172137258 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
2.otbn_sec_cm.27092623304099417511203176162233572868878324169374683222463740920484023184503
Line 84, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 1729454 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 1729454 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 1729454 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 1729454 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 1729454 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
... and 1 more failures.
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 3 failures:
7.otbn_escalate.23542626229467255960922286375142842696363840089702969230698170877621463740784
Line 116, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/7.otbn_escalate/latest/run.log
UVM_ERROR @ 1663268 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 1663268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.otbn_escalate.52067093755177759761199123473430328187665356388697277310242276524363095260338
Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/22.otbn_escalate/latest/run.log
UVM_ERROR @ 5890578 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 5890578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:
0.otbn_sec_wipe_err.8052114864076348226825282946270619867428603342295935562410441307085747183173
Line 123, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 39278854 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 39278854 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 39278854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_sec_wipe_err.30242613025926419707312123367402392919284164942161204284038973236824465806774
Line 109, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 138213860 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 138213860 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 138213860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 2 failures:
2.otbn_partial_wipe.37429533044803512078454776280792467331092331670113630154502889841927185327025
Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 12644772 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 12644772 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 12644772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.otbn_partial_wipe.93549168107693710647600487256326421907824094406532739916121659681090819018335
Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/5.otbn_partial_wipe/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 3470136 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 3470136 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3470136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
3.otbn_stress_all_with_rand_reset.20827880619418506064673651143630655621868686002923617625278142163023606762804
Line 351, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2284985556 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 2284985556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_stress_all_with_rand_reset.41968988133227936665019280675581975510801037753507924286986485027733990067152
Line 285, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 320007627 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 320007627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:
Test otbn_rnd_sec_cm has 1 failures.
3.otbn_rnd_sec_cm.100234959209919670856498217039590329760779637044364069459728756818920006577662
Line 132, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_rnd_sec_cm/latest/run.log
UVM_FATAL @ 167244997 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 167244997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_multi has 1 failures.
8.otbn_multi.35192217023462409857451011793641189683537371377725180664282147377910571262099
Line 159, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_multi/latest/run.log
UVM_FATAL @ 131450116 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 131450116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
14.otbn_passthru_mem_tl_intg_err.47838057375317726805795230715920498929341096529567466048574630949507294211977
Line 113, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/14.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 215111692 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 215111692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
1.otbn_stress_all_with_rand_reset.3129370996191276370844321515735515982349572483260852585693425679623379383437
Line 163, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 93945574 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 93945574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,969): Assertion OnlyWriteLoadDataBignumWhenDMemValid_A has failed has 1 failures:
1.otbn_ctrl_redun.95918850203315064895725656018133043939718200538238941948269166770126915354539
Line 109, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,969): (time 46609516 PS) Assertion tb.dut.u_otbn_core.OnlyWriteLoadDataBignumWhenDMemValid_A has failed
UVM_ERROR @ 46609516 ps: (otbn_core.sv:969) [ASSERT FAILED] OnlyWriteLoadDataBignumWhenDMemValid_A
UVM_INFO @ 46609516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---