1f7db17| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 7.000s | 68.802us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 156.463us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 2.000s | 13.221us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 4.000s | 1251.003us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 2.000s | 80.752us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 2.000s | 59.405us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 2.000s | 13.221us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 2.000s | 80.752us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 3482.000s | 600000.000us | 24 | 50 | 48.00 |
| V2 | cnt_rollover | cnt_rollover | 96.000s | 16365.594us | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 2.000s | 72.575us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 10634.000s | 2798969.492us | 19 | 50 | 38.00 |
| V2 | alert_test | pattgen_alert_test | 2.000s | 106.809us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 2.000s | 72.597us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 3.000s | 114.129us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 3.000s | 114.129us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 156.463us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 13.221us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 80.752us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 7.000s | 30.250us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 156.463us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 13.221us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 80.752us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 7.000s | 30.250us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 283 | 340 | 83.24 | |||
| V2S | tl_intg_err | pattgen_sec_cm | 2.000s | 68.015us | 5 | 5 | 100.00 |
| pattgen_tl_intg_err | 3.000s | 329.166us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 3.000s | 329.166us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 186.000s | 26276.674us | 4 | 50 | 8.00 |
| V3 | TOTAL | 4 | 50 | 8.00 | |||
| Unmapped tests | pattgen_inactive_level | 245.000s | 10002.189us | 30 | 50 | 60.00 | |
| TOTAL | 447 | 570 | 78.42 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.53 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 96.95 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 46 failures:
0.pattgen_stress_all_with_rand_reset.60635832638914807975694647384464164207527084261906254251805720919389329790970
Line 150, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1895411154 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1895441214 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1895441214 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1895761214 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.48802706899950675478782675822124930135335432824779466048601439650315086598836
Line 115, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1094102639 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1094107750 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1094107750 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1094138054 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 44 more failures.
Job timed out after * minutes has 26 failures:
0.pattgen_perf.54460126945185953530152728306118329581415196675182058545851951810933007018088
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Job timed out after 60 minutes
3.pattgen_perf.2129603524210634613726378250477304735407134719247714464697278384845923194704
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 13 more failures.
1.pattgen_stress_all.54755075237723742928504063731278034749769189702589602381366436091300716442820
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
3.pattgen_stress_all.501229927970772033091134038327682479424638216314267592070342110458582778702
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 9 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 18 failures:
2.pattgen_stress_all.14819487500623164972200743003201791351148708176980182120707389664398325735099
Line 151, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
UVM_ERROR @ 25468534895 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11533
4.pattgen_stress_all.57804949710387927189559788809920748983550603284386607886165766329505330053426
Line 127, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log
UVM_ERROR @ 69145231 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10193
... and 16 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 12 failures:
2.pattgen_perf.17606779915446095551783973160895723007175108248495970585398460640496954311413
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.pattgen_perf.98834224316141394611979438842212379372944084284672662739345093891833868076104
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
26.pattgen_stress_all.67105391788280278458775220143148067071875160234441191143334463552482230120145
Line 108, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 4 failures:
0.pattgen_inactive_level.85883995777815826048333543391878940722225007636720359049598812106440740073211
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10061875917 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa25eed90, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10061875917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.pattgen_inactive_level.106487612770881037513058571871783571630955935464678938824852254222587672921431
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10049293519 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb1b10d10, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10049293519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 3 failures:
10.pattgen_inactive_level.66358674954961645183648861189852151353391427636392516272463313786927311870952
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10055866078 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8c85be10, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10055866078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.pattgen_inactive_level.41642646682311886207957729797737690094018617521117893664122161811532763127303
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10131101127 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa3082690, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10131101127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 3 failures:
29.pattgen_inactive_level.103498374006905068080197386625011167764174256375167890132736839297900063810857
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/29.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10843543906 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x47b216d0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10843543906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.pattgen_inactive_level.44139234666602642913920781938388997854280188629822748104229637435481241195423
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10068729877 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9fc66510, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10068729877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
3.pattgen_inactive_level.98709197992901669796770696710383994108151998332992024693213453736260700782476
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10010833605 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb1057290, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10010833605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.pattgen_inactive_level.20463296309919608827147978067433355576903927364766656158799615456848358999015
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10009458907 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xce06ec90, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10009458907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 1 failures:
0.pattgen_stress_all.4242172872387400130267503383625466881922647885429177712004231689216883120190
Line 126, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 1398010271 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
5.pattgen_inactive_level.4955579889646306250099611829336443202787093578082969729604643128655253127150
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10018041024 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc58bb490, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10018041024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
13.pattgen_inactive_level.51573609577147398385100794898604848783420422186366309299133697468694621908951
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10043026282 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x907ff410, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10043026282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
17.pattgen_inactive_level.78265628065831329585657556285756398170916751768876586948667911266724324634249
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10027261219 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb781fbd0, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10027261219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
18.pattgen_inactive_level.41714465806480255159057826099082400831387029907689803301487795307001807488146
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10049195781 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x76f1b10, Comparison=CompareOpEq, exp_data=0x0, call_count=24)
UVM_INFO @ 10049195781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
27.pattgen_inactive_level.57954136179375884388963283770040259416829128780736445410906235333521492931367
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10126909183 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x6a2b16d0, Comparison=CompareOpEq, exp_data=0x0, call_count=26)
UVM_INFO @ 10126909183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
30.pattgen_inactive_level.11271062421210326297989330568866495823322898291449630731066224098231792154978
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10009761218 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x69bcee90, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10009761218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
34.pattgen_inactive_level.20958530931995016415464696836107739972932663367733352093829520773144254454680
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10033403020 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x8404a390, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10033403020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
44.pattgen_inactive_level.74042102258635094731380528324306118827390208968186218168771252020517855448460
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002189064 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x64c82150, Comparison=CompareOpEq, exp_data=0x0, call_count=4)
UVM_INFO @ 10002189064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---