ROM_CTRL/32KB Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: `1f7db17`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.660s	218.676us	4	4	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.680s	1081.289us	10	10	100.00
V1	csr_rw	rom_ctrl_csr_rw	17.050s	4136.499us	40	40	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.410s	4155.129us	10	10	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	12.430s	302.773us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.320s	546.989us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	17.050s	4136.499us	40	40	100.00
		rom_ctrl_csr_aliasing	12.430s	302.773us	10	10	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.870s	289.406us	10	10	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.510s	4006.838us	10	10	100.00
V1		TOTAL			134	134	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	11.170s	316.181us	4	4	100.00
V2	stress_all	rom_ctrl_stress_all	47.010s	13567.542us	40	40	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	24.300s	2107.733us	4	4	100.00
V2	alert_test	rom_ctrl_alert_test	14.090s	1076.954us	100	100	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	16.400s	3991.213us	40	40	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	16.400s	3991.213us	40	40	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.680s	1081.289us	10	10	100.00
		rom_ctrl_csr_rw	17.050s	4136.499us	40	40	100.00
		rom_ctrl_csr_aliasing	12.430s	302.773us	10	10	100.00
		rom_ctrl_same_csr_outstanding	14.870s	309.275us	40	40	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.680s	1081.289us	10	10	100.00
		rom_ctrl_csr_rw	17.050s	4136.499us	40	40	100.00
		rom_ctrl_csr_aliasing	12.430s	302.773us	10	10	100.00
		rom_ctrl_same_csr_outstanding	14.870s	309.275us	40	40	100.00
V2		TOTAL			228	228	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	332.010s	27863.651us	36	40	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	69.230s	5986.301us	40	40	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	317.390s	2477.540us	0	10	0.00
		rom_ctrl_tl_intg_err	145.200s	3068.368us	40	40	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	317.390s	2477.540us	0	10	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	317.390s	2477.540us	0	10	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	332.010s	27863.651us	36	40	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	332.010s	27863.651us	36	40	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	332.010s	27863.651us	36	40	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	332.010s	27863.651us	36	40	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	332.010s	27863.651us	36	40	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	317.390s	2477.540us	0	10	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	317.390s	2477.540us	0	10	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.660s	218.676us	4	4	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.660s	218.676us	4	4	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.660s	218.676us	4	4	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	145.200s	3068.368us	40	40	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	332.010s	27863.651us	36	40	90.00
		rom_ctrl_kmac_err_chk	24.300s	2107.733us	4	4	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	332.010s	27863.651us	36	40	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	332.010s	27863.651us	36	40	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	332.010s	27863.651us	36	40	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	69.230s	5986.301us	40	40	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	317.390s	2477.540us	0	10	0.00
V2S		TOTAL			116	130	89.23
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	523.830s	20585.802us	40	40	100.00
V3		TOTAL			40	40	100.00
		TOTAL			518	532	97.37

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.29	99.46	95.39	99.59	100.00	99.27	95.49	98.81

Failure Buckets

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'

has 8 failures:

Test rom_ctrl_sec_cm has 8 failures.

0.rom_ctrl_sec_cm.97893526325485025391180235261745215041102801125026714265642124940951308794389
Line 114, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 3956475ps failed at 3956475ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 3956475ps failed at 3956475ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

1.rom_ctrl_sec_cm.26457430738215310973477334223794331825986091487852482266615777073861811251146
Line 171, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 18355231ps failed at 18355231ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 18355231ps failed at 18355231ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

... and 6 more failures.

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 4 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 4 failures.
  - 0.rom_ctrl_corrupt_sig_fatal_chk.55603592569158401787398666401859464414106164423254700801214152464941452287414
    Line 97, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 1505758839 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 1505758839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.rom_ctrl_corrupt_sig_fatal_chk.67629032997875670712057733086744026465854311095616770999556126522791462281327
    Line 102, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 1234887948 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 1234887948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:

Test rom_ctrl_sec_cm has 2 failures.

4.rom_ctrl_sec_cm.80405918926098791454193574837772507808679603647658744554815594709558361089253
Line 291, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 23750881ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 23750881ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
  Starting assertion attempts at time 23750881ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))

0.rom_ctrl_sec_cm.111785637024048366303731717102991408949510582188540469565426654634884280932178
Line 165, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 12364090ps failed at 12364090ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 12374507ps failed at 12374507ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'