RV_TIMER Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: `1f7db17`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.330s	173.544us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.910s	16.689us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.890s	13.280us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.500s	334.327us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.050s	28.964us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.050s	19.454us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.890s	13.280us	20	20	100.00
		rv_timer_csr_aliasing	1.050s	28.964us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	11.560s	51785.025us	1	20	5.00
V2	disabled	rv_timer_disabled	4.310s	1592.022us	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	276.040s	199080.016us	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	276.040s	199080.016us	10	10	100.00
V2	stress	rv_timer_stress_all	9.320s	3915.764us	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.890s	14.889us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.850s	18.919us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.610s	796.519us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.610s	796.519us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.910s	16.689us	5	5	100.00
		rv_timer_csr_rw	0.890s	13.280us	20	20	100.00
		rv_timer_csr_aliasing	1.050s	28.964us	5	5	100.00
		rv_timer_same_csr_outstanding	0.990s	315.979us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.910s	16.689us	5	5	100.00
		rv_timer_csr_rw	0.890s	13.280us	20	20	100.00
		rv_timer_csr_aliasing	1.050s	28.964us	5	5	100.00
		rv_timer_same_csr_outstanding	0.990s	315.979us	20	20	100.00
V2		TOTAL			191	210	90.95
V2S	tl_intg_err	rv_timer_sec_cm	1.150s	179.754us	5	5	100.00
		rv_timer_tl_intg_err	1.550s	130.989us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.550s	130.989us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.630s	102.580us	3	10	30.00
V3	max_value	rv_timer_max	2.200s	703.134us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	52.860s	49141.784us	11	20	55.00
V3		TOTAL			14	40	35.00
		TOTAL			305	350	87.14

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.32	100.00	100.00	100.00	--	100.00	96.82	99.12

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 26 failures:
- Test rv_timer_random_reset has 19 failures.
  - 0.rv_timer_random_reset.71774501947705131466365116511546748914114318447251396677717851188415056648447
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @  77324074 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x74d7a904) == 0x1
  UVM_INFO @  77324074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.81524143257203347711463301144347284611435595959372539955092511903292638701402
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 240268470 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2bd63b04) == 0x1
  UVM_INFO @ 240268470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
- Test rv_timer_min has 7 failures.
  - 1.rv_timer_min.88308244264554333810519262349486381472747173852921486367466508349645419969452
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 102579590 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8d598904) == 0x1
  UVM_INFO @ 102579590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.rv_timer_min.80395882711484025890278488435929529195283453880823146325400001377359520053195
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/3.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 632238243 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc655df04) == 0x1
  UVM_INFO @ 632238243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
- Test rv_timer_max has 9 failures.
  - 0.rv_timer_max.51260792071687646301961938907318587745673192073321136785211976839522607666835
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @  85171968 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  85171968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.58103824205602755510511844104260034645793754489918146412699350888146299944715
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @  44843972 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  44843972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 7 failures:
- Test rv_timer_stress_all_with_rand_reset has 7 failures.
  - 0.rv_timer_stress_all_with_rand_reset.101045623393682404400612239967820046128767102180524988296490691023452331830511
    Line 301, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2878974819 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 2878974819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_stress_all_with_rand_reset.45208457874088527308570294928503262098303783694160908152404755940299720856812
    Line 194, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1247957898 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 1247957898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test rv_timer_stress_all_with_rand_reset has 2 failures.

6.rv_timer_stress_all_with_rand_reset.59175589587433966124880220528120039001445784542068629708914360317269899818766
Line 152, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4526365778 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4526365778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.rv_timer_stress_all_with_rand_reset.89412383698104235477431162884701352536987643269261965099733182883796253001252
Line 206, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/8.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 24987326305 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 24987326305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:
- Test rv_timer_max has 1 failures.
  - 7.rv_timer_max.57858787865663714948791097139236362382939810911194883680714390085485927159245
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/7.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 703134363 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
  UVM_INFO @ 703134363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```