SPI_DEVICE/1R1W Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: `1f7db17`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	558.830s	164867.611us	99	100	99.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	97.050us	10	10	100.00
V1	csr_rw	spi_device_csr_rw	2.600s	351.458us	40	40	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.570s	5495.004us	10	10	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.050s	18051.482us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.140s	508.556us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.600s	351.458us	40	40	100.00
		spi_device_csr_aliasing	17.050s	18051.482us	10	10	100.00
V1	mem_walk	spi_device_mem_walk	0.950s	126.676us	10	10	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.930s	120.096us	10	10	100.00
V1		TOTAL			229	230	99.57
V2	csb_read	spi_device_csb_read	1.210s	25.419us	100	100	100.00
V2	mem_parity	spi_device_mem_parity	1.480s	32.547us	20	40	50.00
V2	mem_cfg	spi_device_ram_cfg	1.140s	16.866us	1	2	50.00
V2	tpm_read	spi_device_tpm_rw	11.270s	306.565us	100	100	100.00
V2	tpm_write	spi_device_tpm_rw	11.270s	306.565us	100	100	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	30.330s	9043.914us	100	100	100.00
		spi_device_tpm_sts_read	1.490s	115.947us	100	100	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.290s	11614.708us	100	100	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.520s	12009.539us	100	100	100.00
		spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	41.080s	130283.214us	100	100	100.00
		spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	41.080s	130283.214us	100	100	100.00
		spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	cmd_info_slots	spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	cmd_read_status	spi_device_intercept	25.630s	3118.593us	100	100	100.00
		spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	cmd_read_jedec	spi_device_intercept	25.630s	3118.593us	100	100	100.00
		spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	cmd_read_sfdp	spi_device_intercept	25.630s	3118.593us	100	100	100.00
		spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	cmd_fast_read	spi_device_intercept	25.630s	3118.593us	100	100	100.00
		spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	cmd_read_pipeline	spi_device_intercept	25.630s	3118.593us	100	100	100.00
		spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	flash_cmd_upload	spi_device_upload	44.880s	54292.564us	100	100	100.00
V2	mailbox_command	spi_device_mailbox	106.510s	20524.459us	100	100	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	106.510s	20524.459us	100	100	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	106.510s	20524.459us	100	100	100.00
V2	cmd_read_buffer	spi_device_flash_mode	33.660s	17212.759us	100	100	100.00
		spi_device_read_buffer_direct	16.230s	4524.888us	100	100	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	106.510s	20524.459us	100	100	100.00
		spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	quad_spi	spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	dual_spi	spi_device_flash_all	406.020s	167180.792us	99	100	99.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.740s	29541.244us	100	100	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.740s	29541.244us	100	100	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	558.830s	164867.611us	99	100	99.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	522.020s	284600.003us	100	100	100.00
V2	stress_all	spi_device_stress_all	1286.270s	162537.754us	100	100	100.00
V2	alert_test	spi_device_alert_test	1.130s	46.917us	100	100	100.00
V2	intr_test	spi_device_intr_test	1.020s	52.435us	100	100	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.510s	255.859us	40	40	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.510s	255.859us	40	40	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	97.050us	10	10	100.00
		spi_device_csr_rw	2.600s	351.458us	40	40	100.00
		spi_device_csr_aliasing	17.050s	18051.482us	10	10	100.00
		spi_device_same_csr_outstanding	3.870s	911.844us	40	40	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	97.050us	10	10	100.00
		spi_device_csr_rw	2.600s	351.458us	40	40	100.00
		spi_device_csr_aliasing	17.050s	18051.482us	10	10	100.00
		spi_device_same_csr_outstanding	3.870s	911.844us	40	40	100.00
V2		TOTAL			1900	1922	98.86
V2S	tl_intg_err	spi_device_tl_intg_err	17.120s	4173.061us	40	40	100.00
		spi_device_sec_cm	1.780s	93.714us	10	10	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.120s	4173.061us	40	40	100.00
V2S		TOTAL			50	50	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	394.830s	72871.023us	99	100	99.00
		TOTAL			2278	2302	98.96

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.38	99.12	96.56	83.54	89.36	98.42	94.43	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.103923945103778299030346316968776367396229222350667349532569058945019182422685
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @  28172413 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[11])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @  28172413 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @  28172413 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[907])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.112335438612479923577117892262833474022650308364729427480388384135474172664035
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3764748 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[34])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3764748 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3764748 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[930])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 2 failures:

Test spi_device_flash_and_tpm has 1 failures.

2.spi_device_flash_and_tpm.62115139680459737626800651087946945996747076524635240025344309212380334458229
Line 114, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 42106552995 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (9584640 [0x924000] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x924000 != exp 0x0
  tl_ul_fuzzy_flash_status_q[i] = 0x286e5c
  tl_ul_fuzzy_flash_status_q[i] = 0x1beb08
  UVM_INFO @ 43139280995 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 8/12
  UVM_INFO @ 43139280995 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 9/12

Test spi_device_flash_all has 1 failures.

39.spi_device_flash_all.114321301401335382701485620866573317313479483957043591865641608568701129713260
Line 83, in log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/39.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 7470912895 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (12492800 [0xbea000] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xbea000 != exp 0x0
  tl_ul_fuzzy_flash_status_q[i] = 0xda7234
  tl_ul_fuzzy_flash_status_q[i] = 0x731bc0
  UVM_INFO @ 9693092895 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 3/8
  UVM_INFO @ 9693092895 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 4/8

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.48652129594944224193252252352305331538496194456372373435674627717733475610107
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   1595356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x10f481 [100001111010010000001] vs 0x0 [0])
  UVM_ERROR @   1685356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x22afa8 [1000101010111110101000] vs 0x0 [0])
  UVM_ERROR @   1704356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x50d591 [10100001101010110010001] vs 0x0 [0])
  UVM_ERROR @   1789356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x56e82e [10101101110100000101110] vs 0x0 [0])
  UVM_ERROR @   1806356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe0508f [111000000101000010001111] vs 0x0 [0])

UVM_ERROR (spi_device_scoreboard.sv:2810) [scoreboard] Check failed upload_cmd_q.size == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 18.spi_device_flash_mode_ignore_cmds.27722576188960156972458082919980517099554598605307080842957593292019060726878
    Line 115, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_ERROR @ 33157106366 ps: (spi_device_scoreboard.sv:2810) [uvm_test_top.env.scoreboard] Check failed upload_cmd_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 33157106366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```