SPI_HOST Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: `1f7db17`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	98.000s	5775.577us	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	18.281us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	16.132us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	232.771us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	103.784us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	45.940us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	16.132us	20	20	100.00
		spi_host_csr_aliasing	2.000s	103.784us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	14.894us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	255.409us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	32.000s	55.573us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	52.000s	3795.098us	50	50	100.00
		spi_host_error_cmd	32.000s	29.127us	50	50	100.00
		spi_host_event	232.000s	127679.083us	50	50	100.00
V2	clock_rate	spi_host_speed	39.000s	257.856us	50	50	100.00
V2	speed	spi_host_speed	39.000s	257.856us	50	50	100.00
V2	chip_select_timing	spi_host_speed	39.000s	257.856us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	111.000s	4549.967us	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	32.000s	186.034us	50	50	100.00
V2	cpol_cpha	spi_host_speed	39.000s	257.856us	50	50	100.00
V2	full_cycle	spi_host_speed	39.000s	257.856us	50	50	100.00
V2	duplex	spi_host_smoke	98.000s	5775.577us	50	50	100.00
V2	tx_rx_only	spi_host_smoke	98.000s	5775.577us	50	50	100.00
V2	stress_all	spi_host_stress_all	1002.000s	1000000.000us	48	50	96.00
V2	spien	spi_host_spien	513.000s	109239.123us	50	50	100.00
V2	stall	spi_host_status_stall	750.000s	42003.980us	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	58.000s	3238.404us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	52.000s	3795.098us	50	50	100.00
V2	alert_test	spi_host_alert_test	32.000s	14.135us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	45.171us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	156.885us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	156.885us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	18.281us	5	5	100.00
		spi_host_csr_rw	2.000s	16.132us	20	20	100.00
		spi_host_csr_aliasing	2.000s	103.784us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	17.653us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	18.281us	5	5	100.00
		spi_host_csr_rw	2.000s	16.132us	20	20	100.00
		spi_host_csr_aliasing	2.000s	103.784us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	17.653us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_sec_cm	32.000s	442.788us	5	5	100.00
		spi_host_tl_intg_err	2.000s	208.191us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	208.191us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	638.000s	58506.775us	10	10	100.00
		TOTAL			836	840	99.52

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.16	96.82	93.35	98.69	94.25	88.02	100.00	95.21	90.42

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_host_stress_all has 2 failures.
  - 13.spi_host_stress_all.29941197012145551983323376053971905830067078061173461043764556731650911086086
    Line 126, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.spi_host_stress_all.16151657153398928379914881188836255183354856343826401953252683453020225795589
    Line 142, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/15.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 2 failures:

Test spi_host_status_stall has 2 failures.

16.spi_host_status_stall.47297165667303195705066284903150167401017744229566980907636541438593207113606
Line 17018, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/16.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 55531891423 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 55531891423 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=55531891000 ps
  UVM_INFO @ 55531891423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.spi_host_status_stall.31179575756646620934836145477591569343812191097231142784416158463785662051534
Line 729, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/26.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 344652663 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 344652663 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=344653000 ps
  UVM_INFO @ 344652663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---