SRAM_CTRL/MAIN Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: `1f7db17`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	112.790s	299.480us	100	100	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.020s	43.303us	10	10	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.080s	15.410us	40	40	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.400s	119.663us	10	10	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.150s	20.595us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.830s	4444.572us	37	40	92.50
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.080s	15.410us	40	40	100.00
		sram_ctrl_csr_aliasing	1.150s	20.595us	10	10	100.00
V1	mem_walk	sram_ctrl_mem_walk	341.440s	66410.873us	100	100	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	214.120s	98614.076us	100	100	100.00
V1		TOTAL			407	410	99.27
V2	multiple_keys	sram_ctrl_multiple_keys	1708.670s	27639.390us	100	100	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	419.280s	12962.594us	100	100	100.00
V2	bijection	sram_ctrl_bijection	2341.670s	2000000.000us	99	100	99.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1591.670s	63924.037us	100	100	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	151.290s	177947.264us	100	100	100.00
V2	executable	sram_ctrl_executable	1311.010s	221009.680us	100	100	100.00
V2	partial_access	sram_ctrl_partial_access	107.580s	2536.489us	100	100	100.00
		sram_ctrl_partial_access_b2b	695.540s	50960.962us	100	100	100.00
V2	max_throughput	sram_ctrl_max_throughput	108.900s	802.922us	100	100	100.00
		sram_ctrl_throughput_w_partial_write	112.750s	816.641us	100	100	100.00
		sram_ctrl_throughput_w_readback	105.690s	4575.286us	100	100	100.00
V2	regwen	sram_ctrl_regwen	1355.590s	102924.663us	100	100	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.160s	374.008us	100	100	100.00
V2	stress_all	sram_ctrl_stress_all	7075.490s	328760.393us	100	100	100.00
V2	alert_test	sram_ctrl_alert_test	1.080s	25.841us	100	100	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.940s	138.456us	40	40	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.940s	138.456us	40	40	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.020s	43.303us	10	10	100.00
		sram_ctrl_csr_rw	1.080s	15.410us	40	40	100.00
		sram_ctrl_csr_aliasing	1.150s	20.595us	10	10	100.00
		sram_ctrl_same_csr_outstanding	1.300s	41.050us	40	40	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.020s	43.303us	10	10	100.00
		sram_ctrl_csr_rw	1.080s	15.410us	40	40	100.00
		sram_ctrl_csr_aliasing	1.150s	20.595us	10	10	100.00
		sram_ctrl_same_csr_outstanding	1.300s	41.050us	40	40	100.00
V2		TOTAL			1579	1580	99.94
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	50.270s	27211.597us	39	40	97.50
V2S	tl_intg_err	sram_ctrl_sec_cm	1.260s	16.223us	0	10	0.00
		sram_ctrl_tl_intg_err	4.050s	1970.913us	40	40	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.260s	16.223us	0	10	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.050s	1970.913us	40	40	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1355.590s	102924.663us	100	100	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1355.590s	102924.663us	100	100	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.080s	15.410us	40	40	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1311.010s	221009.680us	100	100	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1311.010s	221009.680us	100	100	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1311.010s	221009.680us	100	100	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	151.290s	177947.264us	100	100	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	10.200s	6028.105us	89	100	89.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	50.270s	27211.597us	39	40	97.50
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	12.480s	9417.124us	68	100	68.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	112.790s	299.480us	100	100	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	112.790s	299.480us	100	100	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1311.010s	221009.680us	100	100	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.260s	16.223us	0	10	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	151.290s	177947.264us	100	100	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.260s	16.223us	0	10	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.260s	16.223us	0	10	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	112.790s	299.480us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.260s	16.223us	0	10	0.00
V2S		TOTAL			236	290	81.38
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	752.900s	6620.364us	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			2321	2380	97.52

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.36	99.11	92.78	90.71	100.00	97.77	95.83	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 32 failures:
- Test sram_ctrl_readback_err has 32 failures.
  - 0.sram_ctrl_readback_err.73199545310093423389074370119720363388314166148064738481844156418560439599507
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 656881988 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x74) != exp (0x30)
  UVM_INFO @ 656881988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.sram_ctrl_readback_err.84172251430863829340499963138805244108184647038531150389288081665578612363461
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 1321587750 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x69) != exp (0x9)
  UVM_INFO @ 1321587750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 30 more failures.
Offending 'reqfifo_rvalid' has 11 failures:
- Test sram_ctrl_mubi_enc_err has 11 failures.
  - 7.sram_ctrl_mubi_enc_err.86334356685155279409122648224010974472914449215047724597535640464294484964726
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 661493262 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 661493262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.sram_ctrl_mubi_enc_err.38909546725918864122964601030356059240667061623896121209943957770889496689059
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 1257016594 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 1257016594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 5 failures:
- Test sram_ctrl_sec_cm has 5 failures.
  - 1.sram_ctrl_sec_cm.25211860822751894804919427013223715583931606696779561854577447418761831736091
    Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @  15718348 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  15718348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 0.sram_ctrl_sec_cm.55973483654899100996998315380049324023776398898114757793852192156951671565346
    Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @  26138555 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  26138555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
Offending '(!$isunknown(rdata_o))' has 3 failures:
- Test sram_ctrl_sec_cm has 3 failures.
  - 0.sram_ctrl_sec_cm.57445911037645855287833949507794672256366171916447674876078744853877207685793
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   5032034 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   5032034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.sram_ctrl_sec_cm.93910520696383474268478880790296209594467472302585923896010010659284497149855
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   3562620 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3562620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 7.sram_ctrl_csr_mem_rw_with_rand_reset.46563024591141121703404193551618102407137800640433502794894115176137955899673
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 134775774 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (10 [0xa] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 134775774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 16.sram_ctrl_csr_mem_rw_with_rand_reset.64122653011926987286295871527758731853063743006342174832770017110892940981970
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  29611641 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2 [0x2] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  29611641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 4.sram_ctrl_bijection.6622278755194901210296312042462802957120723593853556309372818927982722980603
    Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test sram_ctrl_sec_cm has 1 failures.

4.sram_ctrl_sec_cm.49734826031168475180090438554679657671612641668938522845685277794556898309420
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  UVM_ERROR @   5559890 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   5559890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 13.sram_ctrl_passthru_mem_tl_intg_err.98356150683809804028959123787930405283727283994973886344744813715165520842944
    Line 105, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 5652366890 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 5652366890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(depth_o <= *'(Depth))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 4.sram_ctrl_sec_cm.103776206862505052031491709611963626830508159364562086049325907983721462271988
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @ 164859116 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @ 164859116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 16.sram_ctrl_stress_all_with_rand_reset.74273748028877689968489110931043939277018050793530861153206279622583347289179
    Line 564, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1955436364 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1955436364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 17.sram_ctrl_csr_mem_rw_with_rand_reset.19064549005046471931290904774735096135243806244990496255240226168300697661714
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 227256665 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @ 227256665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```