CHIP Simulation Results

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: `1f7db17`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	156.090s	2565.441us	3	3	100.00
		chip_sw_example_rom	102.270s	2547.658us	3	3	100.00
		chip_sw_example_manufacturer	183.750s	3313.217us	3	3	100.00
		chip_sw_example_concurrency	214.080s	3187.198us	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	355.540s	5654.811us	5	5	100.00
V1	csr_rw	chip_csr_rw	634.470s	6433.291us	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	515.350s	5027.814us	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	5243.640s	38928.836us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	777.510s	12296.803us	7	20	35.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	5243.640s	38928.836us	5	5	100.00
		chip_csr_rw	634.470s	6433.291us	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.810s	224.535us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	389.570s	3794.636us	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	389.570s	3794.636us	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	389.570s	3794.636us	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	519.280s	4189.095us	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	519.280s	4189.095us	5	5	100.00
		chip_sw_uart_tx_rx_idx1	566.440s	4985.752us	5	5	100.00
		chip_sw_uart_tx_rx_idx2	460.820s	3833.905us	5	5	100.00
		chip_sw_uart_tx_rx_idx3	553.930s	4299.677us	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	2252.810s	12929.819us	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1389.370s	8937.155us	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1521.560s	13485.105us	5	5	100.00
V1		TOTAL			207	220	94.09
V2	chip_pin_mux	chip_padctrl_attributes	289.640s	6225.386us	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	289.640s	6225.386us	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	221.990s	3033.053us	2	3	66.67
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	387.850s	5961.729us	2	3	66.67
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	261.690s	4022.107us	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1140.780s	13743.850us	5	5	100.00
		chip_tap_straps_testunlock0	441.880s	5938.959us	5	5	100.00
		chip_tap_straps_rma	356.690s	4760.409us	5	5	100.00
		chip_tap_straps_prod	1094.470s	12521.849us	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	176.210s	2316.518us	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	994.420s	9064.047us	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	619.170s	6298.890us	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	619.170s	6298.890us	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	761.850s	7490.500us	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	3080.390s	21795.998us	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	473.440s	3543.455us	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	781.850s	6086.265us	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	4257.810s	18490.049us	3	3	100.00
		chip_sw_aes_enc_jitter_en	225.780s	2873.467us	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	981.220s	8297.557us	3	3	100.00
		chip_sw_hmac_enc_jitter_en	235.130s	3862.507us	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1986.130s	12862.386us	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	239.140s	3557.586us	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	434.150s	4920.848us	3	3	100.00
		chip_sw_clkmgr_jitter	188.400s	2398.354us	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	309.120s	3612.011us	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	640.770s	7168.690us	4	5	80.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	344.910s	4594.388us	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	184.030s	2659.108us	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	344.910s	4594.388us	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	166.320s	3396.789us	3	3	100.00
		chip_sw_aes_smoketest	217.640s	3113.512us	3	3	100.00
		chip_sw_aon_timer_smoketest	264.060s	3361.450us	3	3	100.00
		chip_sw_clkmgr_smoketest	234.590s	3158.104us	3	3	100.00
		chip_sw_csrng_smoketest	241.470s	2741.101us	3	3	100.00
		chip_sw_entropy_src_smoketest	1421.290s	7277.914us	3	3	100.00
		chip_sw_gpio_smoketest	235.550s	2481.329us	3	3	100.00
		chip_sw_hmac_smoketest	282.570s	3129.256us	3	3	100.00
		chip_sw_kmac_smoketest	242.910s	3100.769us	3	3	100.00
		chip_sw_otbn_smoketest	1799.820s	10199.165us	3	3	100.00
		chip_sw_pwrmgr_smoketest	350.500s	5328.416us	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	395.710s	5677.103us	3	3	100.00
		chip_sw_rv_plic_smoketest	226.410s	3146.429us	3	3	100.00
		chip_sw_rv_timer_smoketest	215.160s	2439.012us	3	3	100.00
		chip_sw_rstmgr_smoketest	215.230s	2549.470us	3	3	100.00
		chip_sw_sram_ctrl_smoketest	214.770s	2866.245us	3	3	100.00
		chip_sw_uart_smoketest	256.710s	3564.080us	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	241.380s	3346.992us	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	446.970s	5587.191us	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	12076.870s	62001.267us	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	3593.960s	15010.372us	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	1074.240s	15088.185us	2	3	66.67
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	234.390s	3222.678us	0	3	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	275.440s	3609.421us	0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	10948.640s	55390.569us	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	11289.720s	58302.547us	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	252.540s	4236.181us	2	30	6.67
V2	tl_d_illegal_access	chip_tl_errors	252.540s	4236.181us	2	30	6.67
V2	tl_d_outstanding_access	chip_csr_aliasing	5243.640s	38928.836us	5	5	100.00
		chip_same_csr_outstanding	3254.850s	31218.661us	20	20	100.00
		chip_csr_hw_reset	355.540s	5654.811us	5	5	100.00
		chip_csr_rw	634.470s	6433.291us	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	5243.640s	38928.836us	5	5	100.00
		chip_same_csr_outstanding	3254.850s	31218.661us	20	20	100.00
		chip_csr_hw_reset	355.540s	5654.811us	5	5	100.00
		chip_csr_rw	634.470s	6433.291us	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	83.380s	2514.647us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.140s	53.901us	100	100	100.00
		xbar_smoke_large_delays	108.000s	10545.412us	100	100	100.00
		xbar_smoke_slow_rsp	97.880s	6148.264us	100	100	100.00
		xbar_random_zero_delays	51.930s	607.063us	100	100	100.00
		xbar_random_large_delays	497.650s	56481.833us	100	100	100.00
		xbar_random_slow_rsp	424.280s	29843.576us	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	57.850s	1427.877us	100	100	100.00
		xbar_error_and_unmapped_addr	52.700s	1448.548us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	71.460s	2230.820us	100	100	100.00
		xbar_error_and_unmapped_addr	52.700s	1448.548us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	119.220s	3129.980us	100	100	100.00
		xbar_access_same_device_slow_rsp	984.580s	91278.226us	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	74.340s	2425.096us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	484.540s	19845.486us	100	100	100.00
		xbar_stress_all_with_error	465.380s	15677.065us	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	661.550s	17941.578us	100	100	100.00
		xbar_stress_all_with_reset_error	616.050s	18266.500us	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	3593.960s	15010.372us	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	3451.450s	27878.990us	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	3670.960s	15857.030us	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2936.770s	14663.654us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	3733.010s	15623.792us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	3679.100s	15350.197us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	3650.070s	17000.953us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	3378.770s	14897.278us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28.940s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	24.880s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	19.120s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.480s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	18.970s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	18.780s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	24.150s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	21.340s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	23.650s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.660s	10.320us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.200s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	20.920s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	20.600s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.830s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	20.060s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.630s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.610s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.380s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	20.050s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	21.250s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.860s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	21.370s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	22.880s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	21.240s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	20.420s	10.260us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	2867.810s	11764.485us	3	3	100.00
		rom_e2e_asm_init_dev	3905.980s	16499.060us	3	3	100.00
		rom_e2e_asm_init_prod	3778.120s	16407.378us	3	3	100.00
		rom_e2e_asm_init_prod_end	3877.890s	16383.191us	3	3	100.00
		rom_e2e_asm_init_rma	3797.280s	15058.060us	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	3617.240s	14870.670us	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	3571.100s	14691.276us	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	3800.110s	15342.640us	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	4014.980s	18331.883us	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	0.000s	0.000us	0	3	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	0.000s	0.000us	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	212.080s	2686.302us	3	3	100.00
		chip_sw_aes_enc_jitter_en	225.780s	2873.467us	3	3	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	242.750s	2797.255us	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	197.020s	2927.189us	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	1819.560s	11736.735us	3	3	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	247.620s	3350.272us	0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	467.100s	5285.458us	3	3	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	598.750s	5960.130us	93	100	93.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	721.230s	5577.551us	3	3	100.00
		chip_plic_all_irqs_10	371.120s	3296.785us	3	3	100.00
		chip_plic_all_irqs_20	495.400s	3988.508us	3	3	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	252.480s	3757.889us	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	1501.200s	12218.921us	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	463.130s	5195.974us	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	251.780s	2976.326us	0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	0.000s	0.000us	0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	1606.720s	9412.675us	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	1454.900s	8825.781us	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	1110.340s	7419.266us	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11552.900s	256237.598us	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	336.110s	4183.480us	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	350.500s	5328.416us	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	336.110s	4183.480us	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	621.390s	8372.858us	2	3	66.67
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	621.390s	8372.858us	2	3	66.67
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	462.910s	7213.667us	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	501.720s	4690.518us	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	800.470s	6218.731us	3	3	100.00
		chip_sw_aes_idle	197.020s	2927.189us	3	3	100.00
		chip_sw_hmac_enc_idle	229.210s	3036.350us	3	3	100.00
		chip_sw_kmac_idle	232.140s	3315.662us	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	351.540s	3896.728us	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	409.150s	4228.564us	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	364.320s	5116.609us	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	427.350s	5433.722us	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	1113.380s	10578.941us	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	521.130s	4339.660us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	450.490s	4227.421us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	480.560s	4653.451us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	532.120s	5130.523us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	548.090s	3939.272us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	480.960s	4341.823us	3	3	100.00
		chip_sw_ast_clk_outputs	761.850s	7490.500us	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	439.450s	6383.015us	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	480.560s	4653.451us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	532.120s	5130.523us	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	473.440s	3543.455us	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	781.850s	6086.265us	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	4257.810s	18490.049us	3	3	100.00
		chip_sw_aes_enc_jitter_en	225.780s	2873.467us	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	981.220s	8297.557us	3	3	100.00
		chip_sw_hmac_enc_jitter_en	235.130s	3862.507us	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1986.130s	12862.386us	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	239.140s	3557.586us	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	434.150s	4920.848us	3	3	100.00
		chip_sw_clkmgr_jitter	188.400s	2398.354us	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	198.630s	3153.599us	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	461.610s	4872.010us	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	798.490s	6902.588us	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4505.640s	23844.291us	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	188.290s	2976.213us	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	209.450s	3210.446us	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	825.060s	8323.078us	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	196.820s	2792.847us	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	444.220s	5244.707us	3	3	100.00
		chip_sw_flash_init_reduced_freq	1464.670s	22945.299us	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	4507.470s	26903.275us	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	761.850s	7490.500us	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	489.330s	5367.859us	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	372.920s	3497.879us	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	598.750s	5960.130us	93	100	93.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	1606.720s	9412.675us	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	1149.400s	7159.837us	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	286.310s	3187.245us	1	3	33.33
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	678.280s	7469.519us	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	254.460s	2347.770us	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	6445.870s	29598.472us	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	195.940s	2587.583us	3	3	100.00
		chip_sw_edn_entropy_reqs	1070.140s	7667.575us	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	195.940s	2587.583us	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	1149.400s	7159.837us	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	217.120s	2995.457us	3	3	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	1738.580s	25592.538us	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	758.180s	5608.084us	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	781.850s	6086.265us	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	465.120s	3891.510us	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	473.440s	3543.455us	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	4784.480s	44255.632us	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	1738.580s	25592.538us	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	293.070s	3599.559us	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	1993.970s	12903.584us	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	343.090s	4035.877us	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	4784.480s	44255.632us	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	343.090s	4035.877us	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	343.090s	4035.877us	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	343.090s	4035.877us	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	343.090s	4035.877us	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	598.750s	5960.130us	93	100	93.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	657.940s	16210.921us	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	665.710s	5541.103us	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	502.310s	5146.227us	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	502.310s	5146.227us	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	182.980s	2928.124us	3	3	100.00
		chip_sw_hmac_enc_jitter_en	235.130s	3862.507us	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	229.210s	3036.350us	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	1914.060s	11351.959us	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	449.940s	3853.756us	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	529.280s	5117.827us	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	643.260s	5817.412us	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	503.550s	5912.828us	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	375.510s	4386.388us	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	1993.970s	12903.584us	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1986.130s	12862.386us	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	2112.980s	11730.602us	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	1819.560s	11736.735us	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	3550.170s	16169.005us	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	189.270s	3196.147us	3	3	100.00
		chip_sw_kmac_mode_kmac	289.190s	3429.715us	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	239.140s	3557.586us	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	1993.970s	12903.584us	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	988.690s	11441.305us	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	176.400s	2424.940us	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	1810.440s	10386.865us	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	232.140s	3315.662us	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	467.100s	5285.458us	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1140.780s	13743.850us	5	5	100.00
		chip_tap_straps_rma	356.690s	4760.409us	5	5	100.00
		chip_tap_straps_prod	1094.470s	12521.849us	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	230.820s	3120.067us	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	988.690s	11441.305us	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	988.690s	11441.305us	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	988.690s	11441.305us	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	2189.220s	11920.035us	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_prim_tl_access	657.940s	16210.921us	3	3	100.00
		chip_rv_dm_lc_disabled	216.710s	7741.621us	0	3	0.00
		chip_sw_flash_ctrl_lc_rw_en	343.090s	4035.877us	3	3	100.00
		chip_sw_flash_rma_unlocked	4784.480s	44255.632us	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	244.870s	3283.523us	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	691.140s	7448.863us	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	825.950s	8621.388us	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	738.640s	6436.824us	0	3	0.00
		chip_sw_lc_ctrl_transition	988.690s	11441.305us	15	15	100.00
		chip_sw_keymgr_key_derivation	1993.970s	12903.584us	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	462.560s	8588.745us	3	3	100.00
		chip_sw_sram_ctrl_execution_main	600.270s	7192.747us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	439.450s	6383.015us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	521.130s	4339.660us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	450.490s	4227.421us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	480.560s	4653.451us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	532.120s	5130.523us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	548.090s	3939.272us	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	480.960s	4341.823us	3	3	100.00
		chip_tap_straps_dev	1140.780s	13743.850us	5	5	100.00
		chip_tap_straps_rma	356.690s	4760.409us	5	5	100.00
		chip_tap_straps_prod	1094.470s	12521.849us	5	5	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	172.720s	3189.011us	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	89.030s	3701.544us	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	94.510s	2674.053us	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2444.560s	27074.477us	2	3	66.67
V2	chip_lc_test_locked	chip_rv_dm_lc_disabled	216.710s	7741.621us	0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	2352.080s	35304.395us	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	5529.880s	51088.613us	3	3	100.00
		chip_sw_lc_walkthrough_prod	5607.350s	50416.685us	3	3	100.00
		chip_sw_lc_walkthrough_prodend	730.540s	9076.296us	3	3	100.00
		chip_sw_lc_walkthrough_rma	5246.410s	46451.492us	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	2352.080s	35304.395us	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	90.350s	2773.120us	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	83.010s	2702.150us	3	3	100.00
		rom_volatile_raw_unlock	96.020s	2673.562us	3	3	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	4212.470s	17052.719us	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	4257.810s	18490.049us	3	3	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	800.470s	6218.731us	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	800.470s	6218.731us	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	800.470s	6218.731us	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	390.070s	3481.916us	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	988.690s	11441.305us	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	1738.580s	25592.538us	3	3	100.00
		chip_sw_otbn_mem_scramble	390.070s	3481.916us	3	3	100.00
		chip_sw_keymgr_key_derivation	1993.970s	12903.584us	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	569.440s	4808.116us	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	184.860s	3515.077us	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	1738.580s	25592.538us	3	3	100.00
		chip_sw_otbn_mem_scramble	390.070s	3481.916us	3	3	100.00
		chip_sw_keymgr_key_derivation	1993.970s	12903.584us	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	569.440s	4808.116us	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	184.860s	3515.077us	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	988.690s	11441.305us	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	426.030s	5545.152us	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	230.820s	3120.067us	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_prim_tl_access	657.940s	16210.921us	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	244.870s	3283.523us	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	691.140s	7448.863us	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	825.950s	8621.388us	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	738.640s	6436.824us	0	3	0.00
		chip_sw_lc_ctrl_transition	988.690s	11441.305us	15	15	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	657.940s	16210.921us	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1357.510s	9098.252us	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	503.820s	7829.764us	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	1703.800s	28504.832us	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	429.420s	7772.202us	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	341.390s	7063.817us	0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	610.050s	7206.211us	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1389.470s	23241.707us	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1054.710s	13913.339us	2	3	66.67
		chip_sw_aon_timer_wdog_bite_reset	621.390s	8372.858us	2	3	66.67
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	966.000s	12607.628us	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	537.100s	5893.094us	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	503.820s	7829.764us	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	360.460s	4743.453us	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	525.710s	7804.181us	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	407.260s	7131.348us	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	371.370s	6462.252us	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1831.700s	22453.930us	1	3	33.33
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	883.510s	8002.028us	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	1376.900s	13480.436us	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	2139.910s	30580.414us	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	250.520s	2988.090us	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	598.750s	5960.130us	93	100	93.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	462.560s	8588.745us	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	462.560s	8588.745us	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	1376.900s	13480.436us	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	1831.700s	22453.930us	1	3	33.33
		chip_sw_pwrmgr_wdog_reset	537.100s	5893.094us	3	3	100.00
		chip_sw_pwrmgr_smoketest	350.500s	5328.416us	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	397.990s	4404.199us	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	266.350s	4730.151us	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	382.710s	5345.438us	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	1501.200s	12218.921us	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	167.160s	2587.842us	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	598.750s	5960.130us	93	100	93.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	1454.900s	8825.781us	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	655.030s	4538.956us	3	3	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	647.210s	5168.954us	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	254.030s	2734.439us	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	184.860s	3515.077us	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	266.350s	4730.151us	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	266.350s	4730.151us	0	3	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	1969.090s	20034.967us	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	1283.600s	14185.909us	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	397.990s	4404.199us	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	409.250s	4519.801us	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	329.320s	6353.267us	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	356.690s	4760.409us	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	216.710s	7741.621us	0	3	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	721.230s	5577.551us	3	3	100.00
		chip_plic_all_irqs_10	371.120s	3296.785us	3	3	100.00
		chip_plic_all_irqs_20	495.400s	3988.508us	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	213.700s	3116.815us	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	206.180s	2619.999us	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	3593.960s	15010.372us	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	606.850s	6951.458us	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	284.010s	3812.408us	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	280.090s	3526.954us	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	269.970s	3577.004us	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	569.440s	4808.116us	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	434.150s	4920.848us	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	519.210s	7054.451us	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	475.720s	7681.694us	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	600.270s	7192.747us	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	598.750s	5960.130us	93	100	93.00
		chip_sw_data_integrity_escalation	619.170s	6298.890us	6	6	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	883.510s	8002.028us	3	3	100.00
		chip_sw_sysrst_ctrl_reset	1531.410s	24271.938us	2	3	66.67
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	211.010s	3300.950us	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	274.530s	3766.188us	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	459.270s	4136.228us	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	1531.410s	24271.938us	2	3	66.67
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	1531.410s	24271.938us	2	3	66.67
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	978.040s	11562.786us	0	3	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	978.040s	11562.786us	0	3	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	408.580s	6847.805us	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	0.000s	0.000us	0	3	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	202.610s	3486.950us	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	235.720s	3473.782us	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	287.260s	3488.318us	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	370.670s	4065.203us	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	1259.750s	8166.991us	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	6783.410s	31538.119us	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	2291.630s	12361.546us	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	143.840s	2886.694us	1	1	100.00
V2		TOTAL			2457	2657	92.47
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	206.810s	3630.662us	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	164.950s	2423.064us	1	3	33.33
V2S		TOTAL			4	6	66.67
V3	chip_sw_coremark	chip_sw_coremark	14825.870s	72539.801us	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	1387.710s	6370.604us	3	3	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1498.120s	11659.724us	1	1	100.00
		rom_e2e_jtag_debug_dev	203.700s	3935.588us	0	1	0.00
		rom_e2e_jtag_debug_rma	1548.290s	11345.748us	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	310.380s	4813.889us	1	1	100.00
		rom_e2e_jtag_inject_dev	224.510s	3779.577us	1	1	100.00
		rom_e2e_jtag_inject_rma	311.370s	4774.977us	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	17.543s	0.000us	0	3	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	693.800s	5034.324us	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	395.580s	3074.896us	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	983.470s	5515.143us	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	1921.670s	11468.141us	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	327.750s	2654.911us	3	3	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	716.420s	5090.820us	3	3	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	166.410s	3278.761us	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	153.720s	2769.112us	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	326.860s	6337.969us	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	423.450s	4547.368us	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	1376.900s	13480.436us	3	3	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1498.120s	11659.724us	1	1	100.00
		rom_e2e_jtag_debug_dev	203.700s	3935.588us	0	1	0.00
		rom_e2e_jtag_debug_rma	1548.290s	11345.748us	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	478.220s	4652.165us	3	3	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	598.750s	5960.130us	93	100	93.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	0.000s	0.000us	0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	0.000s	0.000us	0	3	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	231.920s	2972.927us	3	3	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	519.280s	4189.095us	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	3844.080s	18911.181us	1	1	100.00
V3		TOTAL			43	51	84.31
	Unmapped tests	chip_sival_flash_info_access	243.360s	2673.752us	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	569.890s	6146.561us	3	3	100.00
		chip_sw_otp_ctrl_rot_auth_config	2685.700s	32897.444us	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	169.710s	2633.727us	3	3	100.00
		chip_sw_otp_ctrl_descrambling	242.720s	3292.192us	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	309.430s	3723.163us	1	3	33.33
		chip_sw_pwrmgr_sleep_wake_5_bug	13.845s	0.000us	0	3	0.00
		chip_sw_flash_ctrl_write_clear	260.550s	3253.319us	3	3	100.00
		TOTAL			2727	2956	92.25

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.73	94.70	93.61	91.71	57.14	94.73	96.93	99.28

Failure Buckets

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 90 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 90 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.19575782517324527287550469112281407550862268957777072934864941966255188713695
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2435.414473 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2435.414473 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_alert_handler_lpg_sleep_mode_alerts.52019846684268171408497660913833566619932882911695581357379580719436045391545
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2821.446944 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2821.446944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 88 more failures.
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 11 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 2 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.37212451911067334598985669050521236014320112683181412379867150145983316972248
    Line 429, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 11668.991000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 11668.991000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4853940208752764855867914983942762506769969091053549094310225287216660403235
    Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 13612.220000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 13612.220000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.12207605617409065423351789967248917341803804938329176095938841795539492414814
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 6302.623000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 6302.623000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 3 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.111367337876216511546316859587215885006670272608840905931364445105981825930902
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 7417.486000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7417.486000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_pwrmgr_deep_sleep_por_reset.9037253388742211107265076742595056026859140285700264104425458453232986378450
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 7063.817000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7063.817000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 3 failures.
  - 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.43758475572934308984243778175859027648127738546072303426391873490230268344416
    Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7804.181500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7804.181500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.105190469398562477858247946549114394266940357484867442684039740193304680427519
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 5794.428000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5794.428000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 1.chip_sw_aon_timer_wdog_bite_reset.55076615597007162652822331424695997440766295155187966837960878056225419485851
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 8186.312000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 8186.312000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.77076151614678014304436905796027471123706729889377230080593271808530595349790
    Line 529, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.81277234716072654034565583367284594594351405979676562682151928827818477482544
    Line 572, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4606855942158147945549385026689809767785420324183454707110786147209278680674
    Line 632, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.26592784683841158032556447627397010648587763567773624453833555591414512944668
    Line 590, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.89976355401915931276078752507750930481411966319799027590725174286880837427471
    Line 620, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
Job timed out after * minutes has 9 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.11504146718666293623310774552421415533340992261592418857661848590114235114560
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job timed out after 120 minutes
```
  - 1.chip_sw_rv_timer_systick_test.19130779380441132941940543984494985832471652834577881351644822164789523959791
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job timed out after 120 minutes
```
  - ... and 1 more failures.
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 3 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.22046094772846765115226547054278477793365489992187168222845026951867272629984
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.13560540226278609253897959058857478568082018718768043239382960969418470534058
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 3 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.55208134528261080829853956531736869494269411759137377453556636757898844476666
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
  - 1.chip_sw_alert_handler_lpg_sleep_mode_pings.17588194050492166455782305738917512332020241252238471467705128270077525447407
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
  - ... and 1 more failures.

Job returned non-zero exit code has 6 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 3 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.9906684938718635789849262319465420308912196599342060786876474219752676816770
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.240s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_pwrmgr_sleep_wake_5_bug.114408063345300108759465430653793901571024026887322228425335889039565190470618
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.909s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.19506634637593969772222543501370575189142690050035229681159878910358722064845
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 7.649s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_self_hash.51420175421299147285757349979687339048008104970784887129967497066299877367508
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.439s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.115223850031558784699756288915276373409969372388253278688350465683374401823582
    Line 509, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.98835519175985819746752862563674144333182732999595778653285187177808306008271
    Line 529, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.66356302806487065409944603277611895426895485908963598499393091888112013616321
    Line 541, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.94373372649754668796054783686875798620289527142371830919974187126962821593099
    Line 537, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.88819720595163583917093262263931892123266633086295317032242630103626442092246
    Line 572, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 5 failures:
- Test chip_sw_all_escalation_resets has 5 failures.
  - 4.chip_sw_all_escalation_resets.10839427032080749883127266667413933803367833437504513611846916228580255839658
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2918.181500 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2918.181500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 16.chip_sw_all_escalation_resets.72460936930521712591948437863191145311313709694532521924750039517112362098535
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2585.068860 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2585.068860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 4 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.53543768067854012270674917657785376261249849192301036652483772900469688776361
    Line 466, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2769.111848 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2769.111848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 2 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.88768815428723355061224452846091336149819994905237702248144224393989645504055
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2725.463256 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2725.463256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_sw_csrng_fuse_en_sw_app_read_test.12417804765505008114572487242272110415265906346285757498236410371195747124455
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3545.625156 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3545.625156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_all_escalation_resets has 1 failures.
  - 55.chip_sw_all_escalation_resets.83301740884953536266858950566033476002166493986381509618068080098828555263825
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3265.964424 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3265.964424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 3 failures:

Test chip_rv_dm_lc_disabled has 3 failures.

0.chip_rv_dm_lc_disabled.96036379134980456328183138963304115827669932605852607510029655583905629406450
Line 231, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 7741.621228 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x107bc read out mismatch
  UVM_INFO @ 7741.621228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_rv_dm_lc_disabled.79711661436336628726366794336966324348274880154145070430038945789261959503164
Line 218, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 7096.354864 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10600 read out mismatch
  UVM_INFO @ 7096.354864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.608015088660561249753610042053082009809436954225004974032779669442774985218
    Line 618, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2664.171432 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2664.171432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.22256505541845452948849813484643919776324648705902079764518536431481840655644
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3812.407964 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3812.407964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 3 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 3 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.16348635386990038535306054903247435031654775694232290363584693615036503650960
    Line 529, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 5365.971620 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 5365.971620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_otp_ctrl_lc_signals_rma.31709781781026747209062713580307024826752919255698808032473847350463792538645
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 7042.757800 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 7042.757800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 3 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 3 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.70607546336323970973341529817204136505713254146853929458499102343249851823737
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11796.161708 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11796.161708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_sysrst_ctrl_ec_rst_l.39202117742389154285043624928442799401750166106931258682132652960596944606035
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11562.785995 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11562.785995 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:

Test chip_sw_power_idle_load has 3 failures.

0.chip_sw_power_idle_load.68084790182880272985266742431876326446385520690218924406818579608997066946223
Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log

  UVM_ERROR @ 3222.678500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3222.678500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_power_idle_load.84663623748472529947933213713077095015531512468963443241105345335044510106122
Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest/run.log

  UVM_ERROR @ 3355.189500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3355.189500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:
- Test chip_sw_power_sleep_load has 3 failures.
  - 0.chip_sw_power_sleep_load.56138522052370401296672177616771322822836793068590811263916562140411027009303
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3609.421500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3609.421500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_power_sleep_load.48011117712661722269324574621656025071005129558695214886291447159782847462160
    Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3098.092000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3098.092000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.27314997228778546982168407783086287906687241743028127147279208372772867451495
    Line 641, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.51550133594315515620157028680060889263440499548342434410288765061477646488818
    Line 521, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.33257549617880318169828257188972709364535341881209822653192264954213231940372
    Line 663, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 2 failures:
- Test chip_sw_alert_test has 2 failures.
  - 0.chip_sw_alert_test.92411118252910108650474228902522612378030499253695185367390081172924412706138
    Line 388, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3350.272126 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3350.272126 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_alert_test.112127817629623994320173851663325606008521558875630434114019785628486591591382
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2595.461044 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2595.461044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 2 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 2 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.101632601469734767953250293059978213313709062173547055018565105568009160982292
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3349.030808 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3349.030808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_sw_pwrmgr_lowpower_cancel.3010867760407981348329053860212221471755882116711635993974121597330825188271
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 4219.471185 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 4219.471185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 2 failures:

Test chip_sw_rv_core_ibex_lockstep_glitch has 2 failures.

0.chip_sw_rv_core_ibex_lockstep_glitch.67434142200844406501536638317034041225983716754539764250698628532634563701319
Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log

  UVM_FATAL @ 2801.092882 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2801.092882 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rv_core_ibex_lockstep_glitch.93470685333252350727293575571635469145051718987047264391061234232767646849191
Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log

  UVM_FATAL @ 2423.064482 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2423.064482 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 2 failures:
- Test chip_sw_ast_clk_rst_inputs has 2 failures.
  - 0.chip_sw_ast_clk_rst_inputs.60882137307457956274752746365770349730091521927465227854866257049761163798607
    Line 429, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19959.574385 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19959.574385 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_sw_ast_clk_rst_inputs.9246216663791676313076383660893414140699684354748538948895448761020067838332
    Line 424, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 20067.731605 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 20067.731605 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1275671919301711203790553461925390492179511541271331229395358157788863951526
    Line 747, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.105832183282655624750458356200230732051346789009700115230644851519016015356510
    Line 637, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.433438482645574863888792510539582319114340398546932585529178750155052013527
    Line 709, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.40645616058765658932837877245038218519923589948542602518076233852198921500126
    Line 576, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32918) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.7783029030861797816711556120151423536889446370376367126723388439663791070333
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2427.386622 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32918) { a_addr: 'h107bc  a_data: 'h2bf7d615  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h4  a_user: 'h18d4b  d_param: 'h0  d_source: 'h2e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2427.386622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31982) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.33464948806614250301624841585907144850977205413370690488338796258400562512845
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2351.342970 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31982) { a_addr: 'h104c4  a_data: 'hcbe2daeb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h11  a_opcode: 'h4  a_user: 'h18175  d_param: 'h0  d_source: 'h11  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2351.342970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40744) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

1.chip_tl_errors.67266903481096837022940241006748596851533753132720990352564273836366390342559
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2547.550624 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40744) { a_addr: 'h10738  a_data: 'h18aaec79  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h32  a_opcode: 'h4  a_user: 'h1b101  d_param: 'h0  d_source: 'h32  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2547.550624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@213652) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

1.chip_csr_mem_rw_with_rand_reset.98054736011386661409488716451424886444946805903718821809818250278910371554501
Line 239, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 6048.337894 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@213652) { a_addr: 'h1065c  a_data: 'hbc8f92a1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h11  a_opcode: 'h4  a_user: 'h18ad2  d_param: 'h0  d_source: 'h11  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 6048.337894 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41960) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

2.chip_tl_errors.64145308821075675345592395170704237081697498614749344076307381440138599779405
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2754.757744 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41960) { a_addr: 'h10598  a_data: 'h5ca6dc2d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h4  a_user: 'h19206  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2754.757744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32214) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

3.chip_tl_errors.30570207515167293129061915515781483464425005636124527214266228786486011552959
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2223.238364 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32214) { a_addr: 'h1066c  a_data: 'hb961c513  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h4  a_user: 'h1b683  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2223.238364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32104) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

3.chip_csr_mem_rw_with_rand_reset.73220363302011323826605072711414259028426956120526983547722087627005208322980
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2805.611656 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32104) { a_addr: 'h10350  a_data: 'h85627e23  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h186ae  d_param: 'h0  d_source: 'h21  d_data: 'h13  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7d  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2805.611656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32360) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

4.chip_csr_mem_rw_with_rand_reset.108357909924099896889236985848116493179794054591192915383984464687621559078905
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2351.809705 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32360) { a_addr: 'h1060c  a_data: 'hdcc29fb5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h4  a_user: 'h186f8  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2351.809705 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33730) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

5.chip_tl_errors.80170504411209853401495559538218035568801299418297105063823174729911973977859
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2389.823288 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33730) { a_addr: 'h10520  a_data: 'h2ba58893  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h18a4a  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2389.823288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32176) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

5.chip_csr_mem_rw_with_rand_reset.3482282079814613880783734931712275381639791453339374871425737014525850004254
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2334.144352 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32176) { a_addr: 'h106b0  a_data: 'ha4b6a01  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h4  a_user: 'h1926f  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2334.144352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36670) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

6.chip_tl_errors.8320160813876231530575758003290922116979113805930764711687671269755855997671
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2284.563512 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36670) { a_addr: 'h106c0  a_data: 'h2c195065  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h186c0  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2284.563512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35970) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

7.chip_tl_errors.91500194043486671304978674096749150325338878188945175894029337598976544307343
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2331.732584 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35970) { a_addr: 'h10514  a_data: 'h5ee17d85  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h1bac9  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2331.732584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31950) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

7.chip_csr_mem_rw_with_rand_reset.88443467511560037144801580344184539827056638792326504596588397541844748361588
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2545.855512 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31950) { a_addr: 'h10484  a_data: 'he03de374  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h4  a_user: 'h1a9f7  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2545.855512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32310) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

8.chip_tl_errors.69926291194091682192592697239362721757704916028498513698459993436242994211717
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2533.208496 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32310) { a_addr: 'h10764  a_data: 'he68f98be  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h1a548  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2533.208496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33404) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

8.chip_csr_mem_rw_with_rand_reset.100464272833245338701921439360270002287763006865575413432078136256318553691171
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2531.528172 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33404) { a_addr: 'h10560  a_data: 'hefacc396  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h19  a_opcode: 'h4  a_user: 'h1a2f7  d_param: 'h0  d_source: 'h19  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2531.528172 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37200) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

9.chip_tl_errors.44113599232756685821873278314562695620301524194695496937925144215497664899544
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1845.658629 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37200) { a_addr: 'h10638  a_data: 'h9b881e26  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h1b676  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1845.658629 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33184) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

10.chip_tl_errors.12855620527974619891285703665939208636941056159212136963855798291822330011695
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2037.726896 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33184) { a_addr: 'h105b0  a_data: 'h5606a0ad  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h32  a_opcode: 'h4  a_user: 'h19e4b  d_param: 'h0  d_source: 'h32  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2037.726896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32286) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

11.chip_tl_errors.69213619701776439001987409052402709928651319895163419864812727317665263016999
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2071.415036 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32286) { a_addr: 'h10504  a_data: 'hf3fcb88  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h4  a_user: 'h19e6f  d_param: 'h0  d_source: 'h37  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2071.415036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32826) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

12.chip_tl_errors.104142708480937268192366691052225621629487994242076072942921063375737648138299
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1883.277815 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32826) { a_addr: 'h1063c  a_data: 'he0445c2f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h1bae2  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1883.277815 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32708) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

12.chip_csr_mem_rw_with_rand_reset.48926624313165161712019998299899763294051157179845415725932974516461730699794
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1729.051751 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32708) { a_addr: 'h107a8  a_data: 'hd2a64065  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h4  a_user: 'h1a50a  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1729.051751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33680) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

13.chip_tl_errors.1579515554721929243496295785834622764928226727687142264602078140718496185749
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2325.912400 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33680) { a_addr: 'h1033c  a_data: 'he10fa317  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h1ae82  d_param: 'h0  d_source: 'h33  d_data: 'h517  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd10  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2325.912400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32384) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

13.chip_csr_mem_rw_with_rand_reset.65642015682956438697469510193747589630952122901972045449424223328927322177922
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2556.776604 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32384) { a_addr: 'h107c0  a_data: 'h317cef86  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h181c0  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2556.776604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33962) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

14.chip_tl_errors.108059170204327301805067703537409065533120486839237030813608213651494873191220
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1978.601291 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33962) { a_addr: 'h105b0  a_data: 'he45c665  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h19e68  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1978.601291 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32802) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

14.chip_csr_mem_rw_with_rand_reset.36729596040348981991341246897374548044377802923809954720415394110070169022362
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1854.994029 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32802) { a_addr: 'h107a8  a_data: 'h309845c9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h1a534  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1854.994029 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33520) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

15.chip_tl_errors.76984939019967808561442817129221758373585678794991345359195410323424011274709
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2460.889498 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33520) { a_addr: 'h107f0  a_data: 'h3a268b5e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h1bdde  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2460.889498 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32868) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

15.chip_csr_mem_rw_with_rand_reset.20549166673223552542269412030317687965132255699408596121367398838114606280705
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2468.612222 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32868) { a_addr: 'h10450  a_data: 'h1873ad9c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h19999  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2468.612222 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33398) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

16.chip_tl_errors.31761872879603839681674702857759834633711669346774986521008142715059696628154
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2331.277911 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33398) { a_addr: 'h1037c  a_data: 'h4cfe134f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h4  a_user: 'h18661  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2331.277911 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39244) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

17.chip_tl_errors.105842320638106197172153357552872614273062781534661628787959268733371821691060
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2186.906314 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39244) { a_addr: 'h10728  a_data: 'h53d8265b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h4  a_user: 'h195e2  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2186.906314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@217590) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

18.chip_csr_mem_rw_with_rand_reset.31812108869013939998349241478154787017147719944801849978206611671847236470060
Line 239, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 5360.502365 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@217590) { a_addr: 'h10504  a_data: 'haa3759e1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7  a_opcode: 'h4  a_user: 'h19e41  d_param: 'h0  d_source: 'h7  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5360.502365 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@138540) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

19.chip_tl_errors.14507205139676610209850085389448586096606819327265286198930643149732562334601
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3084.176529 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@138540) { a_addr: 'h107b8  a_data: 'hbaaf500c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h4  a_user: 'h181ae  d_param: 'h0  d_source: 'h2e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3084.176529 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31952) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

19.chip_csr_mem_rw_with_rand_reset.62398063925324703621526888600505756433686596436497798595704662636702181411619
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1666.582104 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31952) { a_addr: 'h10754  a_data: 'h6c22a17e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h19906  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1666.582104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32796) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

20.chip_tl_errors.33586393570775454740282245361268003143412945455697877417555824866462553839209
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2551.333735 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32796) { a_addr: 'h10740  a_data: 'h4363ae7e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h1b104  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2551.333735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33252) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

21.chip_tl_errors.40531614838194505865105951555537375779288572934346502521460374972494188366918
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2611.397808 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33252) { a_addr: 'h1074c  a_data: 'he80ba85f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h4  a_user: 'h1a907  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2611.397808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35948) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

22.chip_tl_errors.29046667203120022805157353127281960721473767733711694951908690364035359580578
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2271.522804 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35948) { a_addr: 'h10684  a_data: 'h697580d8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h1a295  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2271.522804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40896) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

23.chip_tl_errors.36580662016693884402213992174522079640947278190494808960132807759665572738488
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2718.024875 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40896) { a_addr: 'h107d0  a_data: 'h5b181ea5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2a  a_opcode: 'h4  a_user: 'h1a547  d_param: 'h0  d_source: 'h2a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2718.024875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34434) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

24.chip_tl_errors.74890101030436406907515077007827818135387869186300889160909999857060557075269
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2937.972545 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34434) { a_addr: 'h10760  a_data: 'h9aaac633  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h1a98e  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2937.972545 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37060) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

25.chip_tl_errors.50674833300747399985581636298511475034153909899740562012481968809520749573786
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2146.189730 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37060) { a_addr: 'h106cc  a_data: 'hbc2be55  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h19eed  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2146.189730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36492) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

26.chip_tl_errors.74669628495779444809410519383784033873781299795669175949721312943007956507917
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2230.372328 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36492) { a_addr: 'h10408  a_data: 'h8596be50  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3b  a_opcode: 'h4  a_user: 'h18106  d_param: 'h0  d_source: 'h3b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2230.372328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33626) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

27.chip_tl_errors.79457819169654770384156006123989810193735106692849889428388114621911367492331
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2496.110280 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33626) { a_addr: 'h1033c  a_data: 'h33133bc0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h1aed1  d_param: 'h0  d_source: 'hf  d_data: 'h517  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd10  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2496.110280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40962) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

28.chip_tl_errors.112024474447779484950278169525328133604977993596576531165540193331963286422425
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2541.913845 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40962) { a_addr: 'h107ec  a_data: 'hba0b64b5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h18170  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2541.913845 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35912) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

29.chip_tl_errors.80134824330480231065504800695319751180546723375511576258805299271707371521632
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2897.776479 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35912) { a_addr: 'h10788  a_data: 'h40c65507  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h1bdc9  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2897.776479 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.43337026967253249738284578878158331747526819236861396284948256023775057586850
    Line 781, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3356.180000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3356.180000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(pin_wkup_req_o))' has 1 failures:
- Test chip_sw_sleep_pin_wake has 1 failures.
  - 0.chip_sw_sleep_pin_wake.60654871590104493252390508951428872357901114720312319457601470371512312003872
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log
```
      Offending '(!$isunknown(pin_wkup_req_o))'
  UVM_ERROR @ 3328.572000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
  UVM_INFO @ 3328.572000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.106065216967032025207504661505105621911116995242256582240040787610754175158207
    Line 511, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 32897.444075 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 32897.444075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@81074) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.71169373333066242670576953251496385069057214032848584440501185229226587653185
Line 428, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4316.113158 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@81074) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4316.113158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.52788786930884397393780964165726834489184847403888336863910335531496335943804
    Line 691, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.105263429884346027576745711633335372586082232356825682552703461811326481433515
    Line 709, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.104813177185658825466500238174793044862597139157185671721770829944276117868907
    Line 452, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 3935.587633 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 3935.587633 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:827) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! has 1 failures:
- Test chip_sw_lc_ctrl_rand_to_scrap has 1 failures.
  - 1.chip_sw_lc_ctrl_rand_to_scrap.16172066318955804888178128293943975951174358898013276724944870554331308605520
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
```
  UVM_FATAL @ 27074.476616 us: (chip_sw_base_vseq.sv:827) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!
  UVM_INFO @ 27074.476616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@82010) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

1.chip_sw_rstmgr_cpu_info.53875400364283067192210809852843461459796456193638884071491490828609281937712
Line 413, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4730.151011 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@82010) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4730.151011 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(reset_cause == HwReq)' has 1 failures:
- Test chip_sw_sensor_ctrl_alert has 1 failures.
  - 1.chip_sw_sensor_ctrl_alert.51077426480135026081921848818271518955752915351515724502985301209116776040955
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_alert/latest/run.log
```
      Offending '(reset_cause == HwReq)'
  UVM_ERROR @ 2717.173764 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
  UVM_INFO @ 2717.173764 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@88378) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

2.chip_sw_rstmgr_cpu_info.70994633647142242815369098726436397387850004135454723298367780414279017940166
Line 417, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3204.659727 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@88378) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3204.659727 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 2.chip_sw_alert_test.75993618802658245418533924049344933289759905875985023033742236497362367928248
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3447.334580 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 3447.334580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement has 1 failures:
- Test rom_raw_unlock has 1 failures.
  - 2.rom_raw_unlock.112632486953766381893315689411959219402435502610486357482517808974724108117559
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log
```
  UVM_FATAL @ 15088.184893 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
  UVM_INFO @ 15088.184893 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 60.chip_sw_all_escalation_resets.40380752283708058606694242795752689998598207631995735427035323409156255698639
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3215.766936 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 3215.766936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```