ADC_CTRL Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: `c766185`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	20.870s	6005.949us	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.370s	1010.170us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.880s	522.038us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	121.760s	52180.147us	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.890s	840.058us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.010s	528.851us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.880s	522.038us	20	20	100.00
		adc_ctrl_csr_aliasing	4.890s	840.058us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	1177.250s	494181.543us	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	933.630s	492446.620us	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	1252.510s	491788.656us	48	50	96.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1207.260s	497888.252us	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	1417.190s	662495.058us	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1186.490s	592087.346us	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	1240.330s	488093.907us	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	1168.540s	494707.329us	30	50	60.00
V2	poweron_counter	adc_ctrl_poweron_counter	18.070s	5199.907us	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	129.600s	44388.921us	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	342.270s	134150.897us	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	2574.810s	1221286.320us	48	50	96.00
V2	alert_test	adc_ctrl_alert_test	2.520s	522.185us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.180s	432.711us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.840s	517.857us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.840s	517.857us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.370s	1010.170us	5	5	100.00
		adc_ctrl_csr_rw	2.880s	522.038us	20	20	100.00
		adc_ctrl_csr_aliasing	4.890s	840.058us	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.600s	4880.609us	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.370s	1010.170us	5	5	100.00
		adc_ctrl_csr_rw	2.880s	522.038us	20	20	100.00
		adc_ctrl_csr_aliasing	4.890s	840.058us	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.600s	4880.609us	20	20	100.00
V2		TOTAL			715	740	96.62
V2S	tl_intg_err	adc_ctrl_sec_cm	25.380s	8083.285us	5	5	100.00
		adc_ctrl_tl_intg_err	30.750s	8334.119us	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	30.750s	8334.119us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	24.680s	41027.261us	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			895	920	97.28

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.36	99.05	96.03	100.00	100.00	98.64	95.95	91.83

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 14 failures:
- Test adc_ctrl_clock_gating has 13 failures.
  - 4.adc_ctrl_clock_gating.19011935801057097980888466874571518443206146332024575605101365857306786169569
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 982339484 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 982339484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.adc_ctrl_clock_gating.13101555140922848181671824456761634061674663345888310547540587426863627842081
    Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 167583391223 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 167583391223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
- Test adc_ctrl_stress_all has 1 failures.
  - 30.adc_ctrl_stress_all.73811360323658208850544820510005313721995848641411668733871833856440185673865
    Line 167, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 166299076361 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 166299076361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 7 failures:
- Test adc_ctrl_clock_gating has 5 failures.
  - 10.adc_ctrl_clock_gating.92889211119949858119618586060286745788781672395424212005882288728848883823304
    Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 11.adc_ctrl_clock_gating.71555035666646936037230261318389297919735032982694778605885131842958102072178
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
- Test adc_ctrl_filters_both has 1 failures.
  - 16.adc_ctrl_filters_both.108532962090069276515718372918361985544592959700783266596891686376023401943956
    Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all has 1 failures.
  - 17.adc_ctrl_stress_all.104301532251441253096776232128878420098620700954092804406480135147453839639949
    Line 149, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 4 failures:

Test adc_ctrl_clock_gating has 2 failures.

2.adc_ctrl_clock_gating.81767325595734144351943728176704767428981487998386774695767180001557078850673
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 108332147058 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 108332147058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.adc_ctrl_clock_gating.16253939692567429808482328004736962479022711809555263936973135895528080325701
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 97672792910 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 97672792910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_interrupt has 2 failures.

9.adc_ctrl_filters_interrupt.102360507970529657829623268380170265260365891681746615234763911232530007329394
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 160305397617 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 160305397617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.adc_ctrl_filters_interrupt.100329303513713835381502290109113843371566631643200144966280237290443919661267
Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 485610975403 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 485610975403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---