AES/MASKED Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: `c766185`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	6.000s	79.069us	2	2	100.00
V1	smoke	aes_smoke	7.000s	59.989us	100	100	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	67.201us	10	10	100.00
V1	csr_rw	aes_csr_rw	3.000s	206.941us	40	40	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	514.120us	10	10	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	760.991us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	63.886us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	206.941us	40	40	100.00
		aes_csr_aliasing	4.000s	760.991us	10	10	100.00
V1		TOTAL			212	212	100.00
V2	algorithm	aes_smoke	7.000s	59.989us	100	100	100.00
		aes_config_error	33.000s	1220.845us	100	100	100.00
		aes_stress	31.000s	1565.342us	100	100	100.00
V2	key_length	aes_smoke	7.000s	59.989us	100	100	100.00
		aes_config_error	33.000s	1220.845us	100	100	100.00
		aes_stress	31.000s	1565.342us	100	100	100.00
V2	back2back	aes_stress	31.000s	1565.342us	100	100	100.00
		aes_b2b	36.000s	1708.022us	100	100	100.00
V2	backpressure	aes_stress	31.000s	1565.342us	100	100	100.00
V2	multi_message	aes_smoke	7.000s	59.989us	100	100	100.00
		aes_config_error	33.000s	1220.845us	100	100	100.00
		aes_stress	31.000s	1565.342us	100	100	100.00
		aes_alert_reset	17.000s	1052.039us	100	100	100.00
V2	failure_test	aes_man_cfg_err	6.000s	57.019us	100	100	100.00
		aes_config_error	33.000s	1220.845us	100	100	100.00
		aes_alert_reset	17.000s	1052.039us	100	100	100.00
V2	trigger_clear_test	aes_clear	16.000s	1514.537us	99	100	99.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	415.794us	2	2	100.00
V2	reset_recovery	aes_alert_reset	17.000s	1052.039us	100	100	100.00
V2	stress	aes_stress	31.000s	1565.342us	100	100	100.00
V2	sideload	aes_stress	31.000s	1565.342us	100	100	100.00
		aes_sideload	9.000s	504.336us	100	100	100.00
V2	deinitialization	aes_deinit	11.000s	849.475us	100	100	100.00
V2	stress_all	aes_stress_all	60.000s	3397.141us	20	20	100.00
V2	alert_test	aes_alert_test	5.000s	51.786us	100	100	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	151.034us	40	40	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	151.034us	40	40	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	67.201us	10	10	100.00
		aes_csr_rw	3.000s	206.941us	40	40	100.00
		aes_csr_aliasing	4.000s	760.991us	10	10	100.00
		aes_same_csr_outstanding	3.000s	100.658us	40	40	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	67.201us	10	10	100.00
		aes_csr_rw	3.000s	206.941us	40	40	100.00
		aes_csr_aliasing	4.000s	760.991us	10	10	100.00
		aes_same_csr_outstanding	3.000s	100.658us	40	40	100.00
V2		TOTAL			1001	1002	99.90
V2S	reseeding	aes_reseed	11.000s	448.958us	100	100	100.00
V2S	fault_inject	aes_fi	9.000s	467.952us	99	100	99.00
		aes_control_fi	54.000s	10005.431us	555	600	92.50
		aes_cipher_fi	58.000s	10003.277us	667	700	95.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	198.073us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	198.073us	40	40	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	198.073us	40	40	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	198.073us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	2233.979us	40	40	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	1028.799us	10	10	100.00
		aes_tl_intg_err	4.000s	339.278us	40	40	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	339.278us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	17.000s	1052.039us	100	100	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	198.073us	40	40	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	59.989us	100	100	100.00
		aes_stress	31.000s	1565.342us	100	100	100.00
		aes_alert_reset	17.000s	1052.039us	100	100	100.00
		aes_core_fi	55.000s	10010.787us	137	140	97.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	198.073us	40	40	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	86.755us	100	100	100.00
		aes_stress	31.000s	1565.342us	100	100	100.00
V2S	sec_cm_key_sideload	aes_stress	31.000s	1565.342us	100	100	100.00
		aes_sideload	9.000s	504.336us	100	100	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	86.755us	100	100	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	86.755us	100	100	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	86.755us	100	100	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	86.755us	100	100	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	86.755us	100	100	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	31.000s	1565.342us	100	100	100.00
V2S	sec_cm_key_masking	aes_stress	31.000s	1565.342us	100	100	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	467.952us	99	100	99.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	467.952us	99	100	99.00
		aes_control_fi	54.000s	10005.431us	555	600	92.50
		aes_cipher_fi	58.000s	10003.277us	667	700	95.29
		aes_ctr_fi	5.000s	71.785us	99	100	99.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	467.952us	99	100	99.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	467.952us	99	100	99.00
		aes_control_fi	54.000s	10005.431us	555	600	92.50
		aes_cipher_fi	58.000s	10003.277us	667	700	95.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	58.000s	10003.277us	667	700	95.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	467.952us	99	100	99.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	467.952us	99	100	99.00
		aes_control_fi	54.000s	10005.431us	555	600	92.50
		aes_ctr_fi	5.000s	71.785us	99	100	99.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	467.952us	99	100	99.00
		aes_control_fi	54.000s	10005.431us	555	600	92.50
		aes_cipher_fi	58.000s	10003.277us	667	700	95.29
		aes_ctr_fi	5.000s	71.785us	99	100	99.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	17.000s	1052.039us	100	100	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	467.952us	99	100	99.00
		aes_control_fi	54.000s	10005.431us	555	600	92.50
		aes_cipher_fi	58.000s	10003.277us	667	700	95.29
		aes_ctr_fi	5.000s	71.785us	99	100	99.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	467.952us	99	100	99.00
		aes_control_fi	54.000s	10005.431us	555	600	92.50
		aes_cipher_fi	58.000s	10003.277us	667	700	95.29
		aes_ctr_fi	5.000s	71.785us	99	100	99.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	467.952us	99	100	99.00
		aes_control_fi	54.000s	10005.431us	555	600	92.50
		aes_ctr_fi	5.000s	71.785us	99	100	99.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	467.952us	99	100	99.00
		aes_control_fi	54.000s	10005.431us	555	600	92.50
		aes_cipher_fi	58.000s	10003.277us	667	700	95.29
V2S		TOTAL			1887	1970	95.79
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	51.000s	3808.842us	0	20	0.00
V3		TOTAL			0	20	0.00
		TOTAL			3100	3204	96.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.36	98.60	96.45	99.41	95.46	98.07	100.00	98.36	98.99

Failure Buckets

Job timed out after * minutes has 45 failures:
- Test aes_control_fi has 32 failures.
  - 1.aes_control_fi.110923402481377648471409212995882308471825871433399419223894697888824118086280
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 6.aes_control_fi.47366739333547550371038926539611800984327254046819503651443337219807468247057
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 30 more failures.
- Test aes_ctr_fi has 1 failures.
  - 24.aes_ctr_fi.61876001389969055302192101693469601458468015860005840425966453925611348754382
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/24.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_cipher_fi has 12 failures.
  - 51.aes_cipher_fi.29639909057763520590038886272009483298424126629380708304846458768699342097414
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/51.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 79.aes_cipher_fi.112457420940665346607629780061536646627831233392969350979129717707174940728479
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/79.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 20 failures:
- Test aes_cipher_fi has 20 failures.
  - 70.aes_cipher_fi.97572311011442125445260215092256520450260348607576314928084151868713884833790
    Line 147, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/70.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10025510884 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025510884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 72.aes_cipher_fi.40316021429042461971994939663465257836415136321988495271721128299656793785777
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/72.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016936336 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016936336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 13 failures:

Test aes_stress_all_with_rand_reset has 13 failures.

0.aes_stress_all_with_rand_reset.73751144244774264028260336720920255042855929641908742016162392157539709369646
Line 533, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 388396292 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 388396292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.31138308289127597742672726402992927870504015603149428964577463199023701815264
Line 192, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  83752105 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  83752105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_control_fi has 13 failures.
  - 11.aes_control_fi.17948174983646145575147996901899440874318864059993787676204340809988049017070
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021450329 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021450329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 65.aes_control_fi.31219042681364120250874489605438242012350967647650226498856205246335531929153
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/65.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002212036 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002212036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 4 failures:
- Test aes_stress_all_with_rand_reset has 4 failures.
  - 4.aes_stress_all_with_rand_reset.30087987938110639531708484438362963821864301142120409846529765037438631460015
    Line 162, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 113123491 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 113123491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.67106233466344419639336597583215785127195394307063320035821714186801478571677
    Line 168, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  43550558 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  43550558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.89347012037283705074742822785549281991017507802701787546026038227768327302373
    Line 148, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  44387348 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  44387348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.63614781168123435443434082296058075004287840622706963563691367299204432188443
    Line 425, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 314808225 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 314808225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 43.aes_core_fi.55883727441134307237921479265414033748810655378936254849266536873698659782165
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/43.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004870720 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004870720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.aes_core_fi.106972465335907167871399928145097062598700568359087478298932939210072981188608
    Line 139, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010785276 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010785276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.9471509742781432732264173027749562914284642276881192146491312201666969923047
    Line 150, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 611884385 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 611884385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

5.aes_fi.59449512794687478788350028842808809376448345237969874676152308484005549367532
Line 700, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 9934936 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 9894936 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 9934936 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 9894936 PS)
  UVM_ERROR @   9934936 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 243.aes_cipher_fi.63161123013194841064162431491866346241254269191909001914201452552544437328600
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/243.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @  13153278 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  13153278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 36.aes_clear.111999411775706264450965199867572622389091848159636984057088367837872231862638
    Line 27303, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/36.aes_clear/latest/run.log
```
  UVM_FATAL @  61234189 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 3
           TEST FAILED MESSAGES DID NOT MATCH

                 0 b1 	 e6 	 5c 	 0
                 1 00 	 1e 	 26 	 0
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 52.aes_core_fi.78041364081235257218419800667804833013123031425272336972552697845111668945035
    Line 132, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/52.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010787085 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010787085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```