CSRNG Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: c766185

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	12.000s	17.210us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	43.657us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	185.830us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	20.000s	523.507us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	341.569us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	124.333us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	185.830us	20	20	100.00
		csrng_csr_aliasing	7.000s	341.569us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	20.000s	1333.491us	200	200	100.00
V2	alerts	csrng_alert	71.000s	4041.852us	500	500	100.00
V2	err	csrng_err	14.000s	24.093us	500	500	100.00
V2	cmds	csrng_cmds	418.000s	37750.227us	50	50	100.00
V2	life cycle	csrng_cmds	418.000s	37750.227us	50	50	100.00
V2	stress_all	csrng_stress_all	899.000s	53582.950us	48	50	96.00
V2	intr_test	csrng_intr_test	3.000s	13.052us	50	50	100.00
V2	alert_test	csrng_alert_test	12.000s	44.996us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	18.000s	1779.073us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	18.000s	1779.073us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	43.657us	5	5	100.00
		csrng_csr_rw	4.000s	185.830us	20	20	100.00
		csrng_csr_aliasing	7.000s	341.569us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	334.423us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	43.657us	5	5	100.00
		csrng_csr_rw	4.000s	185.830us	20	20	100.00
		csrng_csr_aliasing	7.000s	341.569us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	334.423us	20	20	100.00
V2		TOTAL			1438	1440	99.86
V2S	tl_intg_err	csrng_sec_cm	24.000s	525.930us	5	5	100.00
		csrng_tl_intg_err	13.000s	1319.397us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	16.502us	50	50	100.00
		csrng_csr_rw	4.000s	185.830us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	71.000s	4041.852us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	899.000s	53582.950us	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
		csrng_sec_cm	24.000s	525.930us	5	5	100.00
V2S	sec_cm_cmd_stage_fsm_sparse	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
		csrng_sec_cm	24.000s	525.930us	5	5	100.00
V2S	sec_cm_ctr_drbg_fsm_sparse	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
		csrng_sec_cm	24.000s	525.930us	5	5	100.00
V2S	sec_cm_ctr_drbg_ctr_redun	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
		csrng_sec_cm	24.000s	525.930us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
		csrng_sec_cm	24.000s	525.930us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	71.000s	4041.852us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	899.000s	53582.950us	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	71.000s	4041.852us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	1319.397us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
		csrng_sec_cm	24.000s	525.930us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
		csrng_sec_cm	24.000s	525.930us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	20.000s	1333.491us	200	200	100.00
		csrng_err	14.000s	24.093us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	311.000s	11887.439us	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1628	1630	99.88

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.51	98.60	96.50	99.47	96.70	93.65	85.19	95.86	91.24

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
  • Test csrng_stress_all has 2 failures.

    • 30.csrng_stress_all.46378147772626714646838989674556441307635080373066049855573972170125354535127
      Line 160, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/30.csrng_stress_all/latest/run.log

        UVM_ERROR @ 18070379170 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 18070379170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 41.csrng_stress_all.42602805455736648984450723432498311275823925407833391044403334962398781694256
      Line 164, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/41.csrng_stress_all/latest/run.log

        UVM_ERROR @ 1770874853 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 1770874853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---