EDN Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: c766185

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.220s	19.405us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.910s	65.291us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.050s	18.321us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.760s	770.847us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.400s	39.995us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.540s	28.907us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.050s	18.321us	20	20	100.00
		edn_csr_aliasing	1.400s	39.995us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	75.910s	4405.965us	300	300	100.00
V2	csrng_commands	edn_genbits	75.910s	4405.965us	300	300	100.00
V2	genbits	edn_genbits	75.910s	4405.965us	300	300	100.00
V2	interrupts	edn_intr	1.240s	20.348us	50	50	100.00
V2	alerts	edn_alert	1.490s	119.885us	200	200	100.00
V2	errs	edn_err	1.320s	22.866us	100	100	100.00
V2	disable	edn_disable	1.170s	12.595us	50	50	100.00
		edn_disable_auto_req_mode	1.530s	46.940us	50	50	100.00
V2	stress_all	edn_stress_all	6.730s	385.835us	50	50	100.00
V2	intr_test	edn_intr_test	0.960s	15.876us	50	50	100.00
V2	alert_test	edn_alert_test	3.670s	497.934us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.220s	195.295us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.220s	195.295us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.910s	65.291us	5	5	100.00
		edn_csr_rw	1.050s	18.321us	20	20	100.00
		edn_csr_aliasing	1.400s	39.995us	5	5	100.00
		edn_same_csr_outstanding	1.320s	141.733us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.910s	65.291us	5	5	100.00
		edn_csr_rw	1.050s	18.321us	20	20	100.00
		edn_csr_aliasing	1.400s	39.995us	5	5	100.00
		edn_same_csr_outstanding	1.320s	141.733us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	7.580s	602.737us	5	5	100.00
		edn_tl_intg_err	2.950s	366.386us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.060s	21.066us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.490s	119.885us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.580s	602.737us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.580s	602.737us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.580s	602.737us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.580s	602.737us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.490s	119.885us	200	200	100.00
		edn_sec_cm	7.580s	602.737us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.490s	119.885us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.950s	366.386us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	109.100s	25148.794us	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1130	1130	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.57	98.87	94.29	96.97	91.86	96.33	97.56	93.13