HMAC Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: c766185

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	10.420s	1745.134us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.330s	40.789us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.240s	32.227us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.150s	1951.825us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.580s	1187.516us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	570.310s	99707.666us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.240s	32.227us	20	20	100.00
		hmac_csr_aliasing	8.580s	1187.516us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	74.480s	1903.112us	10	10	100.00
V2	back_pressure	hmac_back_pressure	88.040s	3682.972us	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	271.480s	30664.206us	30	30	100.00
		hmac_test_sha384_vectors	476.310s	53310.087us	75	75	100.00
		hmac_test_sha512_vectors	540.320s	29969.929us	75	75	100.00
		hmac_test_hmac256_vectors	15.740s	1765.578us	50	50	100.00
		hmac_test_hmac384_vectors	15.720s	359.241us	60	60	100.00
		hmac_test_hmac512_vectors	18.280s	1759.680us	75	75	100.00
V2	burst_wr	hmac_burst_wr	37.400s	14427.860us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	886.560s	19821.376us	10	10	100.00
V2	error	hmac_error	66.100s	9149.088us	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	137.800s	28753.995us	10	10	100.00
V2	save_and_restore	hmac_smoke	10.420s	1745.134us	10	10	100.00
		hmac_long_msg	74.480s	1903.112us	10	10	100.00
		hmac_back_pressure	88.040s	3682.972us	25	25	100.00
		hmac_datapath_stress	886.560s	19821.376us	10	10	100.00
		hmac_burst_wr	37.400s	14427.860us	50	50	100.00
		hmac_stress_all	1789.270s	543333.089us	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	10.420s	1745.134us	10	10	100.00
		hmac_long_msg	74.480s	1903.112us	10	10	100.00
		hmac_back_pressure	88.040s	3682.972us	25	25	100.00
		hmac_datapath_stress	886.560s	19821.376us	10	10	100.00
		hmac_wipe_secret	137.800s	28753.995us	10	10	100.00
		hmac_test_sha256_vectors	271.480s	30664.206us	30	30	100.00
		hmac_test_sha384_vectors	476.310s	53310.087us	75	75	100.00
		hmac_test_sha512_vectors	540.320s	29969.929us	75	75	100.00
		hmac_test_hmac256_vectors	15.740s	1765.578us	50	50	100.00
		hmac_test_hmac384_vectors	15.720s	359.241us	60	60	100.00
		hmac_test_hmac512_vectors	18.280s	1759.680us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	10.420s	1745.134us	10	10	100.00
		hmac_long_msg	74.480s	1903.112us	10	10	100.00
		hmac_back_pressure	88.040s	3682.972us	25	25	100.00
		hmac_datapath_stress	886.560s	19821.376us	10	10	100.00
		hmac_burst_wr	37.400s	14427.860us	50	50	100.00
		hmac_error	66.100s	9149.088us	10	10	100.00
		hmac_wipe_secret	137.800s	28753.995us	10	10	100.00
		hmac_test_sha256_vectors	271.480s	30664.206us	30	30	100.00
		hmac_test_sha384_vectors	476.310s	53310.087us	75	75	100.00
		hmac_test_sha512_vectors	540.320s	29969.929us	75	75	100.00
		hmac_test_hmac256_vectors	15.740s	1765.578us	50	50	100.00
		hmac_test_hmac384_vectors	15.720s	359.241us	60	60	100.00
		hmac_test_hmac512_vectors	18.280s	1759.680us	75	75	100.00
		hmac_stress_all	1789.270s	543333.089us	50	50	100.00
V2	stress_all	hmac_stress_all	1789.270s	543333.089us	50	50	100.00
V2	alert_test	hmac_alert_test	0.970s	39.886us	50	50	100.00
V2	intr_test	hmac_intr_test	0.960s	42.536us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.320s	526.541us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.320s	526.541us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.330s	40.789us	5	5	100.00
		hmac_csr_rw	1.240s	32.227us	20	20	100.00
		hmac_csr_aliasing	8.580s	1187.516us	5	5	100.00
		hmac_same_csr_outstanding	3.050s	190.542us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.330s	40.789us	5	5	100.00
		hmac_csr_rw	1.240s	32.227us	20	20	100.00
		hmac_csr_aliasing	8.580s	1187.516us	5	5	100.00
		hmac_same_csr_outstanding	3.050s	190.542us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.250s	142.054us	5	5	100.00
		hmac_tl_intg_err	4.640s	873.577us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.640s	873.577us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	10.420s	1745.134us	10	10	100.00
V3	stress_reset	hmac_stress_reset	6.420s	117.193us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	513.170s	5247.941us	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.300s	107.665us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.17	99.95	96.80	100.00	100.00	99.83	97.61	100.00