I2C Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: `c766185`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	87.770s	10336.268us	50	50	100.00
V1	target_smoke	i2c_target_smoke	36.150s	2864.165us	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.920s	72.518us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.020s	20.587us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.580s	279.544us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.740s	372.240us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.780s	114.036us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.020s	20.587us	20	20	100.00
		i2c_csr_aliasing	1.740s	372.240us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	4.250s	499.673us	2	50	4.00
V2	host_stress_all	i2c_host_stress_all	2401.070s	57754.084us	8	50	16.00
V2	host_maxperf	i2c_host_perf	1229.470s	69686.439us	49	50	98.00
V2	host_override	i2c_host_override	1.020s	30.406us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	298.510s	35131.618us	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	140.440s	2518.990us	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.620s	223.501us	50	50	100.00
		i2c_host_fifo_fmt_empty	22.130s	1084.463us	50	50	100.00
		i2c_host_fifo_reset_rx	12.140s	258.845us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	190.700s	24851.253us	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	35.850s	1144.833us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	6.440s	337.178us	15	50	30.00
V2	target_glitch	i2c_target_glitch	4.190s	4011.338us	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	1332.190s	77152.281us	50	50	100.00
V2	target_maxperf	i2c_target_perf	9.830s	7090.738us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	67.160s	6438.479us	50	50	100.00
		i2c_target_intr_smoke	9.890s	14592.992us	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.210s	379.325us	50	50	100.00
		i2c_target_fifo_reset_tx	2.550s	289.510us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	1499.330s	68798.887us	50	50	100.00
		i2c_target_stress_rd	67.160s	6438.479us	50	50	100.00
		i2c_target_intr_stress_wr	539.910s	32507.528us	50	50	100.00
V2	target_timeout	i2c_target_timeout	9.780s	2743.575us	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	221.650s	5952.640us	46	50	92.00
V2	bad_address	i2c_target_bad_addr	8.660s	12894.047us	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	44.620s	10006.812us	24	50	48.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.120s	597.421us	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.090s	187.998us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	1229.470s	69686.439us	49	50	98.00
		i2c_host_perf_precise	720.550s	24375.751us	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	35.850s	1144.833us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	14.470s	1018.118us	47	50	94.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.260s	594.348us	50	50	100.00
		i2c_target_nack_acqfull_addr	3.840s	2153.438us	50	50	100.00
		i2c_target_nack_txstretch	2.200s	1506.813us	35	50	70.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	23.470s	1589.765us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.550s	1074.222us	50	50	100.00
V2	alert_test	i2c_alert_test	0.990s	78.394us	50	50	100.00
V2	intr_test	i2c_intr_test	1.010s	16.069us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.860s	243.648us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.860s	243.648us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.920s	72.518us	5	5	100.00
		i2c_csr_rw	1.020s	20.587us	20	20	100.00
		i2c_csr_aliasing	1.740s	372.240us	5	5	100.00
		i2c_same_csr_outstanding	1.340s	194.564us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.920s	72.518us	5	5	100.00
		i2c_csr_rw	1.020s	20.587us	20	20	100.00
		i2c_csr_aliasing	1.740s	372.240us	5	5	100.00
		i2c_same_csr_outstanding	1.340s	194.564us	20	20	100.00
V2		TOTAL			1615	1792	90.12
V2S	tl_intg_err	i2c_sec_cm	1.390s	288.112us	5	5	100.00
		i2c_tl_intg_err	2.120s	90.231us	20	20	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.120s	90.231us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	49.030s	4201.951us	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.560s	217.291us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	18.340s	1007.498us	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1795	2042	87.90

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.22	97.25	89.33	89.66	47.62	93.83	96.41	89.43

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 94 failures:

Test i2c_host_error_intr has 48 failures.

0.i2c_host_error_intr.60674953426766788575673239691334618845090496316761799755414583587785881693591
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @   3578239 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @   3578239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.93326997429292339201026082875564393287910314405049342714463813931222954851774
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  72912252 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  72912252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 46 more failures.

Test i2c_host_stress_all has 27 failures.

1.i2c_host_stress_all.50173349072501327004798453400963860630148708245833796105866353704557463965727
Line 120, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 20173876044 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 20173876044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_host_stress_all.106546299335042182215359960888642123255570180381002053790523850551008553185649
Line 111, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 6669042228 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 6669042228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 25 more failures.

Test i2c_target_stress_all_with_rand_reset has 5 failures.

1.i2c_target_stress_all_with_rand_reset.26237552328347252915247580602225333033392862531698239922850233164213903155757
Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 602521260 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 602521260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.33367214850087207976754600987024805778084560365185006156656425370367186037891
Line 93, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1676177201 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 1676177201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test i2c_host_mode_toggle has 14 failures.

3.i2c_host_mode_toggle.20009868420770230936814988764313364875380985754374853374176754000188297034493
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  98404518 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  98404518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_host_mode_toggle.115666900007598995865964963289175101471478349260550211341883343802516185458717
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  87290235 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  87290235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
- Test i2c_target_hrst has 26 failures.
  - 0.i2c_target_hrst.74631755267387892300035401958079832634805564113159441207250953488741013577915
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10229548290 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10229548290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_hrst.28370989512077533523557634947236984613128460793924267431150917791194465475673
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10004441713 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10004441713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 24 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 25 failures:
- Test i2c_target_unexp_stop has 25 failures.
  - 0.i2c_target_unexp_stop.67280799338589436052136023679288683741479631857561338772252409153708688352019
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  60285874 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 37 [0x25])
  UVM_INFO @  60285874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.9219097134324456058151319289868928596624652529861382072866038850058717378986
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 266773727 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 221 [0xdd])
  UVM_INFO @ 266773727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 23 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 21 failures:

Test i2c_host_stress_all has 12 failures.

0.i2c_host_stress_all.77030749614822533256036623440975555491606491967222205640569265853758183436253
Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 25190195727 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2086629

2.i2c_host_stress_all.6371772517580685671531628932099746525238966610099875906555669408548293669139
Line 132, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 54252411499 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @9101307

... and 10 more failures.

Test i2c_host_mode_toggle has 9 failures.

2.i2c_host_mode_toggle.94690244580914856824108682378669162926728172983615142299459309094295047755856
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 128337473 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @21702

4.i2c_host_mode_toggle.6545445748305487157211300172289803386501660904746679216642953650455039876873
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 158487485 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @37232

... and 7 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
- Test i2c_target_unexp_stop has 17 failures.
  - 3.i2c_target_unexp_stop.85948212617546707444165131469042133811554333429148533835859053102034562211826
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  71284564 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  71284564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_unexp_stop.106650232639948237757662663996957687574658644855896928236050953007115768993245
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  52151918 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  52151918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 15 failures:
- Test i2c_target_nack_txstretch has 15 failures.
  - 1.i2c_target_nack_txstretch.14053536424490166541112128297023098815028960087693125036784299080269344166700
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 257177356 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 257177356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_nack_txstretch.50185318533339106605283077937966373386086525457028584387037298794858673900960
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 1043130578 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 1043130578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.53770018869072858868243416227567426258313382936459809432486000816378044719474
Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1642388696 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1642388696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.47559159260301081455868421052612774444934393238590222386911197422302300759700
Line 115, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 968111259 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 968111259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 3 failures.

2.i2c_target_stress_all_with_rand_reset.36689584315290413102163053827322589691407108099377781266951994430193191594226
Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 338710991 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 338710991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all_with_rand_reset.31831923163275925209378929533946466657552072782438027741472920825128328598853
Line 101, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1007497628 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1007497628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 8 failures:

Test i2c_target_unexp_stop has 8 failures.

4.i2c_target_unexp_stop.53509470631824288440777293454903417262988934653660306976725576506251278135457
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 126363505 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 126363505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.i2c_target_unexp_stop.57763541360081079900979084994672982351785119663077573578977980803615061818660
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 129179170 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 129179170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 8 failures:

Test i2c_host_mode_toggle has 8 failures.

9.i2c_host_mode_toggle.11241110643107975613763703465326554411970209982244413703646103603926393780972
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 188662097 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

12.i2c_host_mode_toggle.40084001509733592321708142468238094495894355417365899666869079707298918383720
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 171602274 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 6 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 0.i2c_target_fifo_watermarks_tx.108473918554654975839886939320346889558683853630813905484860013699103560145702
    Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
- Test i2c_target_tx_stretch_ctrl has 3 failures.
  - 7.i2c_target_tx_stretch_ctrl.92870256531837915883886940224979279537578396432562710116594659703004292343257
    Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 14.i2c_target_tx_stretch_ctrl.20776173793127910136297925002356734183291851505774601660034859309115951922600
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
- Test i2c_target_stretch has 4 failures.
  - 30.i2c_target_stretch.8969792473819911530319364237162034033057213054340416039031793769638472179068
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/30.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10002498148 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10002498148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 33.i2c_target_stretch.1346720537497073636864494495695945511913499027336849223883892656188039310409
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/33.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10001544629 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10001544629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
- Test i2c_host_mode_toggle has 3 failures.
  - 5.i2c_host_mode_toggle.41634361733864281111421419798433664156590179323611477235707115167722569166071
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  58928268 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x15593014, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  58928268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 37.i2c_host_mode_toggle.79651192286896486273105842792511265349559133082701675488800778746380798964914
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/37.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 108888777 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x12a19d94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 108888777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.30665102735427586414142281787031106245977788690357640753052480861290643842469
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 4011337936 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 4011337936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.10109652356327022111650070141724767846858666761784462451351037686398935796751
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 748526056 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 748526056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 0.i2c_target_stress_all_with_rand_reset.114040065358800597586352384468312523473591675939875466626583677887914912724382
    Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 333513035 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 333513035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_stress_all_with_rand_reset.85178239231483882201732690896443836464815739751042906096497479488688382123448
    Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5544420726 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5544420726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 2 failures:
- Test i2c_host_stress_all has 1 failures.
  - 8.i2c_host_stress_all.43743808532925267994104857032085219057250391520795334738532676404550850139618
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_perf has 1 failures.
  - 26.i2c_host_perf.19729618705375026223866573438735778206222357224536322984145339609082709405996
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/26.i2c_host_perf/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 2 failures.

9.i2c_host_stress_all.44166139375097145406262634839626681985836885724971016122292476802621512241272
Line 138, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 102552404438 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @29570383

47.i2c_host_stress_all.33118474244481540316045817177352739170862224839917825328239699361784003698769
Line 148, in log /nightly/current_run/scratch/master/i2c-sim-vcs/47.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 72868042389 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @19292197

Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 24.i2c_host_mode_toggle.14427819815309365403702870962166220160268756028904031512570371685333431181702
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/24.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```