KEYMGR Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: `c766185`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	18.360s	2791.868us	50	50	100.00
V1	random	keymgr_random	86.770s	39663.473us	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.430s	28.675us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.510s	50.358us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.610s	921.699us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.060s	554.197us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.660s	190.275us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.510s	50.358us	20	20	100.00
		keymgr_csr_aliasing	7.060s	554.197us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	96.420s	15812.560us	49	50	98.00
V2	sideload	keymgr_sideload	33.260s	4948.706us	50	50	100.00
		keymgr_sideload_kmac	35.110s	9486.911us	50	50	100.00
		keymgr_sideload_aes	43.970s	9763.453us	49	50	98.00
		keymgr_sideload_otbn	35.210s	7860.876us	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	33.510s	5267.239us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	5.820s	175.402us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.030s	368.710us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	27.660s	5340.716us	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	52.570s	8526.544us	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	14.830s	1398.903us	48	50	96.00
V2	stress_all	keymgr_stress_all	293.290s	74015.588us	49	50	98.00
V2	intr_test	keymgr_intr_test	1.250s	17.459us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.320s	86.496us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.280s	1003.210us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.280s	1003.210us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.430s	28.675us	5	5	100.00
		keymgr_csr_rw	1.510s	50.358us	20	20	100.00
		keymgr_csr_aliasing	7.060s	554.197us	5	5	100.00
		keymgr_same_csr_outstanding	4.580s	833.735us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.430s	28.675us	5	5	100.00
		keymgr_csr_rw	1.510s	50.358us	20	20	100.00
		keymgr_csr_aliasing	7.060s	554.197us	5	5	100.00
		keymgr_same_csr_outstanding	4.580s	833.735us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	tl_intg_err	keymgr_tl_intg_err	11.750s	507.325us	20	20	100.00
		keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.100s	978.385us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.100s	978.385us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.100s	978.385us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.100s	978.385us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	16.160s	1709.724us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.750s	507.325us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.100s	978.385us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	96.420s	15812.560us	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_csr_rw	1.510s	50.358us	20	20	100.00
		keymgr_random	86.770s	39663.473us	50	50	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_csr_rw	1.510s	50.358us	20	20	100.00
		keymgr_random	86.770s	39663.473us	50	50	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_csr_rw	1.510s	50.358us	20	20	100.00
		keymgr_random	86.770s	39663.473us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.820s	175.402us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	52.570s	8526.544us	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	52.570s	8526.544us	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	86.770s	39663.473us	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	20.900s	4683.177us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	27.080s	4225.904us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.820s	175.402us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	27.080s	4225.904us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	27.080s	4225.904us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	27.080s	4225.904us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.210s	717.848us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	27.080s	4225.904us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	18.790s	3400.942us	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1083	1110	97.57

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.60	99.13	97.87	98.29	100.00	99.01	97.72	91.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test keymgr_stress_all_with_rand_reset has 18 failures.
  - 0.keymgr_stress_all_with_rand_reset.103597439950585485320500068953501914704287430525521160151897680162405358447743
    Line 664, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1258714316 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1258714316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.keymgr_stress_all_with_rand_reset.102224414332893183873650095282819971315742205542827834639819455977284048115795
    Line 1171, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 387515481 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 387515481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:
- Test keymgr_sideload_aes has 1 failures.
  - 0.keymgr_sideload_aes.19242634794328481743452771487050027247847812641376180808316865308149081262603
    Line 86, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_aes/latest/run.log
```
  UVM_ERROR @   1884844 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   1884844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 9.keymgr_stress_all_with_rand_reset.91593327837197822006387240367473550800505128244719672432629834889849081921910
    Line 529, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 116092570 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 116092570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 37.keymgr_stress_all.13091597871759735467626911413550650592776699590524619092177508668706225578856
    Line 1985, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/37.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 169013416 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 169013416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 44.keymgr_sync_async_fault_cross.54143682309732768486459303175244852239574130565261299438484145125866898003224
    Line 121, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  12464127 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  12464127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 3.keymgr_stress_all_with_rand_reset.77360730930782095761300741855908551803951149110702850207096412677614307186915
    Line 617, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 565989869 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 565989869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 29.keymgr_sync_async_fault_cross.5825533980711578957540996468850925517477152057845174524132532378121781675036
    Line 179, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  86303365 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  86303365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

35.keymgr_lc_disable.13600216590361812413419312644248399911736877746164411252571379927423980707506
Line 493, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  63012224 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (10305845181382395113327206987403757220579995756217014457081738690053045852639953300334647643415701166447925197961590607576952006703855046893789063599539564 [0xc4c5ec03133f61cb39e8ee35583d98e7973a9f60b5e487f364ee3afdf1f16f8ccf62b1d5d34a69c7c87c866c641ca5ce75a39fe445623f5e98eb72162352c56c] vs 10305845181382395113327206987403757220579995756217014457081738690053045852639953300334647643415701166447925197961590607576952006703855046893789063599539564 [0xc4c5ec03133f61cb39e8ee35583d98e7973a9f60b5e487f364ee3afdf1f16f8ccf62b1d5d34a69c7c87c866c641ca5ce75a39fe445623f5e98eb72162352c56c]) AES key at state StDisabled for Attestation Aes
  UVM_INFO @  63012224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 39.keymgr_stress_all_with_rand_reset.6810559396151227170278445222125230199454068004387792036246965941225568648211
    Line 170, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1145060833 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1145060833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 45.keymgr_cfg_regwen.73106473620705398779210748181754213856388610812277045145586175547436977596493
    Line 134, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @   9614913 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @   9614913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```