KMAC/UNMASKED Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: c766185

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	80.030s	14703.860us	99	100	99.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.370s	33.508us	10	10	100.00
V1	csr_rw	kmac_csr_rw	1.350s	32.098us	40	40	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.720s	9602.589us	10	10	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.790s	1263.599us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.720s	262.110us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.350s	32.098us	40	40	100.00
		kmac_csr_aliasing	7.790s	1263.599us	10	10	100.00
V1	mem_walk	kmac_mem_walk	1.000s	22.949us	10	10	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.260s	36.794us	10	10	100.00
V1		TOTAL			229	230	99.57
V2	long_msg_and_output	kmac_long_msg_and_output	3731.260s	1302153.912us	100	100	100.00
V2	burst_write	kmac_burst_write	1340.550s	15478.666us	100	100	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	2117.470s	252386.138us	10	10	100.00
		kmac_test_vectors_sha3_256	1915.980s	418928.413us	10	10	100.00
		kmac_test_vectors_sha3_384	1910.820s	982383.563us	10	10	100.00
		kmac_test_vectors_sha3_512	1009.910s	43878.225us	10	10	100.00
		kmac_test_vectors_shake_128	2545.950s	105889.441us	10	10	100.00
		kmac_test_vectors_shake_256	1975.170s	121625.542us	10	10	100.00
		kmac_test_vectors_kmac	3.710s	179.720us	10	10	100.00
		kmac_test_vectors_kmac_xof	3.090s	1067.230us	10	10	100.00
V2	sideload	kmac_sideload	459.740s	35047.686us	100	100	100.00
V2	app	kmac_app	341.220s	23421.207us	100	100	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	331.080s	77269.420us	20	20	100.00
V2	entropy_refresh	kmac_entropy_refresh	358.780s	18322.115us	100	100	100.00
V2	error	kmac_error	454.590s	14186.086us	100	100	100.00
V2	key_error	kmac_key_error	20.540s	21755.257us	100	100	100.00
V2	sideload_invalid	kmac_sideload_invalid	157.960s	10074.607us	85	100	85.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.120s	3457.856us	40	40	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.850s	2415.472us	40	40	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	59.640s	5667.923us	20	20	100.00
V2	lc_escalation	kmac_lc_escalation	54.490s	3762.217us	100	100	100.00
V2	stress_all	kmac_stress_all	2411.450s	1161978.198us	100	100	100.00
V2	intr_test	kmac_intr_test	1.120s	61.211us	100	100	100.00
V2	alert_test	kmac_alert_test	1.500s	271.550us	100	100	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.400s	142.987us	40	40	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.400s	142.987us	40	40	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.370s	33.508us	10	10	100.00
		kmac_csr_rw	1.350s	32.098us	40	40	100.00
		kmac_csr_aliasing	7.790s	1263.599us	10	10	100.00
		kmac_same_csr_outstanding	2.440s	102.666us	40	40	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.370s	33.508us	10	10	100.00
		kmac_csr_rw	1.350s	32.098us	40	40	100.00
		kmac_csr_aliasing	7.790s	1263.599us	10	10	100.00
		kmac_same_csr_outstanding	2.440s	102.666us	40	40	100.00
V2		TOTAL			1465	1480	98.99
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.130s	85.052us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.130s	85.052us	40	40	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.130s	85.052us	40	40	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.130s	85.052us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.360s	274.446us	40	40	100.00
V2S	tl_intg_err	kmac_tl_intg_err	4.300s	981.952us	40	40	100.00
		kmac_sec_cm	115.060s	27302.843us	10	10	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.300s	981.952us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.490s	3762.217us	100	100	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	80.030s	14703.860us	99	100	99.00
V2S	sec_cm_key_sideload	kmac_sideload	459.740s	35047.686us	100	100	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.130s	85.052us	40	40	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	115.060s	27302.843us	10	10	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	115.060s	27302.843us	10	10	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	115.060s	27302.843us	10	10	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	80.030s	14703.860us	99	100	99.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.490s	3762.217us	100	100	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	115.060s	27302.843us	10	10	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	343.420s	17920.218us	20	20	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	80.030s	14703.860us	99	100	99.00
V2S		TOTAL			150	150	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	232.690s	5634.325us	15	20	75.00
V3		TOTAL			15	20	75.00
		TOTAL			1859	1880	98.88

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.65	97.69	94.41	100.00	73.55	96.04	97.74	96.12

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 4 failures:

  • Test kmac_stress_all_with_rand_reset has 4 failures.

    • 2.kmac_stress_all_with_rand_reset.51762535270433101626083974181001224684082340916656284081009231797046769152853
      Line 421, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27432931274 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 27432931274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.kmac_stress_all_with_rand_reset.18905472736033230889310512544540848538447581031421138324425174701338420129521
      Line 194, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1908684625 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 1908684625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:

  • Test kmac_sideload_invalid has 3 failures.

    • 0.kmac_sideload_invalid.83300633059542142588287497290445334069234013452930609182941904370627294204421
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10007116739 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7631000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10007116739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.kmac_sideload_invalid.40101756676682920601204430866523167405191976434018719006673840024118746532244
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/6.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10008620127 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa8638000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10008620127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 1.kmac_sideload_invalid.107563432078957913985971768540569424713575413913538085944798649201562691018817
      Line 88, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10092820527 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3def8000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
        UVM_INFO @ 10092820527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 27.kmac_sideload_invalid.8745083356860515782283188094289026056502250053154871660122181767756998758863
      Line 91, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10331242094 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc5cdf000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
        UVM_INFO @ 10331242094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 5.kmac_sideload_invalid.101616257986273435235989689686186912325881998972295799696536590488958610249350
      Line 96, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10369375599 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcb4e2000, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
        UVM_INFO @ 10369375599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 38.kmac_sideload_invalid.71941149346755175020459804478990361356429846909226902750743640025019094414655
      Line 98, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10139076625 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4eb5000, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
        UVM_INFO @ 10139076625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 11.kmac_sideload_invalid.54964335657842079565661984314758307336719122247625278772073204831398985877324
      Line 77, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10171102893 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5691d000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10171102893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 21.kmac_sideload_invalid.24105098732562769200951274221564660974207291739171074119651895519244132863267
      Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10071494115 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe1add000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10071494115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 18.kmac_sideload_invalid.23833043935313442237589303717115323056360203278615141233524440717207852398389
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10164822275 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x514dc000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10164822275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 19.kmac_sideload_invalid.71312657071457022171637545433293522851902298959501176473139690151808127234640
      Line 80, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10046087267 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x89574000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10046087267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 31.kmac_sideload_invalid.49634887798387283617698368557458966633823920605094694851584355059759100295360
      Line 96, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/31.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10234440813 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdc9f7000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
        UVM_INFO @ 10234440813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 37.kmac_sideload_invalid.109662329354427836781211763481076369995321369803018069554538457176790069688493
      Line 97, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/37.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10443726521 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb3537000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
        UVM_INFO @ 10443726521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 32.kmac_sideload_invalid.102459304706252206796255777887214256096148116669719189955671368530781773887953
      Line 85, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10074606630 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa58f7000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
        UVM_INFO @ 10074606630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 43.kmac_sideload_invalid.56133155697725265194547828434759355100886756002775948181861448009487062313271
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10028538552 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7e4c0000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10028538552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 2.kmac_stress_all_with_rand_reset.16267619316502644268341356057952959611095940967992262361186312043520954987112
      Line 142, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2399811365 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2399811365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_smoke has 1 failures.

    • 23.kmac_smoke.62925022936665035703102720631272384275398125066262048481530870182962540739377
      Line 74, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/23.kmac_smoke/latest/run.log

        UVM_ERROR @  55995451 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  55995451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---