c766185| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 10.000s | 198.147us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 82.000s | 2209.505us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 9.000s | 17.054us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 9.000s | 190.763us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 13.000s | 97.349us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 9.000s | 43.478us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 13.000s | 31.432us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 9.000s | 190.763us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 9.000s | 43.478us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 58.000s | 7149.575us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 28.000s | 1459.682us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 561.000s | 2402.392us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 52.000s | 167.375us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 85.000s | 965.817us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 300.000s | 15166.039us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 40.000s | 140.536us | 59 | 60 | 98.33 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 7.000s | 35.588us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 39.000s | 157.865us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 5.000s | 52.220us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 9.000s | 45.380us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 9.000s | 85.751us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 9.000s | 85.751us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 9.000s | 17.054us | 5 | 5 | 100.00 |
| otbn_csr_rw | 9.000s | 190.763us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 9.000s | 43.478us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 9.000s | 15.032us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 9.000s | 17.054us | 5 | 5 | 100.00 |
| otbn_csr_rw | 9.000s | 190.763us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 9.000s | 43.478us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 9.000s | 15.032us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 245 | 246 | 99.59 | |||
| V2S | mem_integrity | otbn_imem_err | 10.000s | 34.024us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.311s | 0.000us | 14 | 15 | 93.33 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 132.000s | 933.620us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 11.000s | 61.986us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 12.000s | 51.677us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 9.000s | 19.102us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 7.000s | 17.794us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 6.000s | 21.175us | 2 | 2 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 7.000s | 24.045us | 9 | 10 | 90.00 |
| V2S | tl_intg_err | otbn_tl_intg_err | 27.000s | 460.042us | 20 | 20 | 100.00 |
| otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 50.000s | 264.779us | 17 | 20 | 85.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 |
| V2S | prim_count_check | otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 10.000s | 198.147us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 16.311s | 0.000us | 14 | 15 | 93.33 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 10.000s | 34.024us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 27.000s | 460.042us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 40.000s | 140.536us | 59 | 60 | 98.33 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 10.000s | 34.024us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.311s | 0.000us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 7.000s | 35.588us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 17.794us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 82.000s | 2209.505us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 10.000s | 34.024us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.311s | 0.000us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 7.000s | 35.588us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 17.794us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 40.000s | 140.536us | 59 | 60 | 98.33 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 10.000s | 34.024us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.311s | 0.000us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 7.000s | 35.588us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 17.794us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 82.000s | 2209.505us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 9.000s | 29.424us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 120.695us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 53.000s | 155.654us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 53.000s | 155.654us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 12.000s | 44.955us | 8 | 10 | 80.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 15.000s | 86.361us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 13.000s | 54.946us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 13.000s | 54.946us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 9.000s | 45.244us | 5 | 7 | 71.43 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 82.000s | 2209.505us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 82.000s | 2209.505us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 82.000s | 2209.505us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 85.000s | 965.817us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 82.000s | 2209.505us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 82.000s | 2209.505us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 12.000s | 88.450us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 82.000s | 2209.505us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 1090.000s | 4647.129us | 3 | 5 | 60.00 |
| V2S | TOTAL | 151 | 163 | 92.64 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 367.000s | 6386.863us | 4 | 10 | 40.00 |
| V3 | TOTAL | 4 | 10 | 40.00 | |||
| TOTAL | 566 | 585 | 96.75 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 99.02 | 99.58 | 95.15 | 99.67 | 93.18 | 93.37 | 97.44 | 96.95 | 100.00 |
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
0.otbn_stress_all_with_rand_reset.51878551745151462275877783256388890675186095122583694691422161458283016045255
Line 169, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2437960378 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2437960378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_stress_all_with_rand_reset.70054472953298111372495876280328068230683360313708965265053449821299412273681
Line 156, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 241522520 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 241522520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:
Test otbn_sec_wipe_err has 2 failures.
1.otbn_sec_wipe_err.38609480436874680995096597741473389820428223307993957666796859344985419031666
Line 111, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32224550 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 32224550 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 32224550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.otbn_sec_wipe_err.59712031784834593328418712092801167042468950454840420516415887476060094900403
Line 111, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 45243521 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 45243521 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 45243521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_ctrl_redun has 1 failures.
11.otbn_ctrl_redun.55610224812370296258718012681497157790511915870198781292869344577799796909095
Line 107, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/11.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 37035568 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 37035568 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 37035568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:
8.otbn_passthru_mem_tl_intg_err.12786023903784332646905112495386753576362218914882910831182365884272415694365
Line 98, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 73291374 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 73291374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.otbn_passthru_mem_tl_intg_err.102982866764511037624602441828390381801666824344284305971058125274333285197635
Line 83, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/14.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 2381174 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 2381174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 2 failures:
0.otbn_sec_cm.13802051701992401378153567381273688287772078553098323213469463578178543390117
Line 105, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 70357617 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 70357617 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 70357617 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 70357617 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 70357617 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
2.otbn_sec_cm.28920176644687001146805983995515446322093045591883710747048498152924041067261
Line 102, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 133998561 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 133998561 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 133998561 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 133998561 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 133998561 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
4.otbn_passthru_mem_tl_intg_err.94766783035277456038530859611015047063660320404261950157937997406616607484865
Line 83, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 3831546 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 3831546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code has 1 failures:
0.otbn_dmem_err.41280057194954132308228803654168963707570005190738791084128121025240865289008
Log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/run.log
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 41280057194954132308228803654168963707570005190738791084128121025240865289008 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=1075950384 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_dmem_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_dmem_err.1075950384 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_dmem_err.1075950384 -covoverwrite' seed=41280057194954132308228803654168963707570005190738791084128121025240865289008 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_dmem_err_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 41280057194954132308228803654168963707570005190738791084128121025240865289008 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest
2025/11/30 13:10:30 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:
2.otbn_partial_wipe.24914521115608794782213962056497835208510244797180228101983773670837850889016
Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 10629588 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 10629588 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 10629588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
4.otbn_rf_base_intg_err.104121607834950094992887380947181648550507220560547651138026351363161899065409
Line 107, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_rf_base_intg_err/latest/run.log
UVM_ERROR @ 69913705 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 69913705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
5.otbn_rf_base_intg_err.12947696287262145148740814820754087581301479501922026096254754878355543756642
Line 107, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/5.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 44100085 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
UVM_INFO @ 44100085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
7.otbn_stress_all_with_rand_reset.3864553628156335568592442501834518086292813593477884473772570553999580260238
Line 206, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1296203930 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1296203930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
36.otbn_escalate.21087098388972826673607687321158185202997616598047806674884966540782428465745
Line 110, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/36.otbn_escalate/latest/run.log
UVM_ERROR @ 2030195 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 2030195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---