c766185| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 6.000s | 121.964us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 22.000s | 42.468us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 20.000s | 14.628us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 7.000s | 1217.623us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 2.000s | 37.177us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 2.000s | 81.594us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 20.000s | 14.628us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 2.000s | 37.177us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 2704.000s | 600000.000us | 28 | 50 | 56.00 |
| V2 | cnt_rollover | cnt_rollover | 87.000s | 2629.161us | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 2.000s | 457.850us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 10006.000s | 10000000.000us | 20 | 50 | 40.00 |
| V2 | alert_test | pattgen_alert_test | 2.000s | 36.529us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 24.000s | 25.757us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 33.000s | 257.566us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 33.000s | 257.566us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 22.000s | 42.468us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 20.000s | 14.628us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 37.177us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 16.043us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 22.000s | 42.468us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 20.000s | 14.628us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 37.177us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 16.043us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 340 | 84.71 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 33.000s | 175.576us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 2.000s | 239.215us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 33.000s | 175.576us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 141.000s | 6937.317us | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 238.000s | 10006.164us | 39 | 50 | 78.00 | |
| TOTAL | 457 | 570 | 80.18 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.53 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 96.95 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:
0.pattgen_stress_all_with_rand_reset.88321355232151710348986918869195935619054533833607788541105575286020583058929
Line 187, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3528594492 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3528617641 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3528617641 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 3528897641 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.17895430209655479818320584044199167188491305142787537181499445569536554127206
Line 251, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2826168507 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2826173724 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2826173724 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 2826257060 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 46 more failures.
Job timed out after * minutes has 20 failures:
9.pattgen_stress_all.70443547542702114957768906128363965596777529147293745057942118628859969814298
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
10.pattgen_stress_all.4225080342325623660577539629218233504568848998767662679305689333044645208393
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 7 more failures.
11.pattgen_perf.2624606522767524157826630163987868545779968530120369543886628916224394750495
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_perf/latest/run.log
Job timed out after 60 minutes
15.pattgen_perf.84777347828945652310726288244624439777711466066477484001728559931138905191978
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 9 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 19 failures:
1.pattgen_stress_all.38993701426063965373816088721097851437651013821077482185083197975199240141174
Line 145, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
UVM_ERROR @ 48466799951 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10262
4.pattgen_stress_all.41472985253410830164071555204328349915820351009481362129850045080359971122358
Line 134, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log
UVM_ERROR @ 85175178 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10141
... and 17 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 12 failures:
7.pattgen_perf.1302765661097905919479213700292954617454663915061283852332623382956411726861
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.pattgen_perf.25398389688833592908462995929709696408779747328688888385222114403305643742605
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
20.pattgen_stress_all.19822891210678696252762538488049833292529840613160587265883538780848085593869
Line 110, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 3 failures:
Test pattgen_stress_all_with_rand_reset has 2 failures.
20.pattgen_stress_all_with_rand_reset.46758844968440925899457143148646624177511917799577850129962708824808473329081
Line 117, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 170609417 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
47.pattgen_stress_all_with_rand_reset.90454743736905774536555558650845723710965068383035169787524816395507099326710
Line 129, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 235791859 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
Test pattgen_stress_all has 1 failures.
25.pattgen_stress_all.16486503374873736333894957845784099954509419158904445456492122699318580413026
Line 115, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_stress_all/latest/run.log
UVM_ERROR @ 127907709 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
-----------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
26.pattgen_inactive_level.45784153556750899163196807281852954643003667187902099433661288553038665442911
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002114369 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe7c46550, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002114369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.pattgen_inactive_level.82693896723842192558842835646328185180218568752081736876838695597172870576375
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002935222 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb9e25150, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002935222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
32.pattgen_inactive_level.73036195261341924248684966301993928539548547104736659886072817864507930967607
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10079539953 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xcbe75ad0, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10079539953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.pattgen_inactive_level.75641177551114772892732350903367884468667800107257569941795767936254390043295
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10009793492 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x258782d0, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10009793492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
3.pattgen_inactive_level.13884758734426099072264604302458320998751095212445612819800889129412162153227
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10017340610 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x2c7a6010, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10017340610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
6.pattgen_inactive_level.92327056290204648203535019871481296096551415915837561687472175881561727139125
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10172791075 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1e92b410, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10172791075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
8.pattgen_inactive_level.54702171866469405709141963171321441599838550581284103302612240063200834225246
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10011213223 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xabf2c350, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10011213223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
17.pattgen_inactive_level.6736167251017687647590896796019769222600006342741034694923441825189355387767
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10062149293 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x817db050, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10062149293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
27.pattgen_inactive_level.34352039660823404333932348731773685938923969421674361483083192404286527857783
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10005983744 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xce289110, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10005983744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
34.pattgen_inactive_level.29233585684561437010754442528912214857213236969670813938594356010570611213202
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10006164100 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe38bedd0, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10006164100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
48.pattgen_inactive_level.94376679449877510301510458340382787823981671018304137256970444414430140695974
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10017166834 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x14c604d0, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10017166834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---