ROM_CTRL/32KB Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: `c766185`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	10.210s	759.492us	4	4	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	19.350s	3986.143us	10	10	100.00
V1	csr_rw	rom_ctrl_csr_rw	12.140s	299.571us	40	40	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.090s	543.177us	10	10	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.590s	2501.736us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	13.700s	310.235us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	12.140s	299.571us	40	40	100.00
		rom_ctrl_csr_aliasing	10.590s	2501.736us	10	10	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.160s	3127.184us	10	10	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.000s	3980.850us	10	10	100.00
V1		TOTAL			134	134	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.860s	311.451us	4	4	100.00
V2	stress_all	rom_ctrl_stress_all	39.090s	752.731us	40	40	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	22.230s	1078.443us	4	4	100.00
V2	alert_test	rom_ctrl_alert_test	12.810s	2029.810us	100	100	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.530s	1169.901us	40	40	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.530s	1169.901us	40	40	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	19.350s	3986.143us	10	10	100.00
		rom_ctrl_csr_rw	12.140s	299.571us	40	40	100.00
		rom_ctrl_csr_aliasing	10.590s	2501.736us	10	10	100.00
		rom_ctrl_same_csr_outstanding	15.490s	1977.746us	40	40	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	19.350s	3986.143us	10	10	100.00
		rom_ctrl_csr_rw	12.140s	299.571us	40	40	100.00
		rom_ctrl_csr_aliasing	10.590s	2501.736us	10	10	100.00
		rom_ctrl_same_csr_outstanding	15.490s	1977.746us	40	40	100.00
V2		TOTAL			228	228	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	310.450s	8599.290us	39	40	97.50
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	58.430s	6886.045us	40	40	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	531.590s	4738.323us	2	10	20.00
		rom_ctrl_tl_intg_err	157.210s	1625.446us	40	40	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	531.590s	4738.323us	2	10	20.00
V2S	prim_count_check	rom_ctrl_sec_cm	531.590s	4738.323us	2	10	20.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	310.450s	8599.290us	39	40	97.50
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	310.450s	8599.290us	39	40	97.50
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	310.450s	8599.290us	39	40	97.50
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	310.450s	8599.290us	39	40	97.50
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	310.450s	8599.290us	39	40	97.50
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	531.590s	4738.323us	2	10	20.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	531.590s	4738.323us	2	10	20.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	10.210s	759.492us	4	4	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	10.210s	759.492us	4	4	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	10.210s	759.492us	4	4	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	157.210s	1625.446us	40	40	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	310.450s	8599.290us	39	40	97.50
		rom_ctrl_kmac_err_chk	22.230s	1078.443us	4	4	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	310.450s	8599.290us	39	40	97.50
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	310.450s	8599.290us	39	40	97.50
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	310.450s	8599.290us	39	40	97.50
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	58.430s	6886.045us	40	40	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	531.590s	4738.323us	2	10	20.00
V2S		TOTAL			121	130	93.08
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	521.110s	4417.788us	40	40	100.00
V3		TOTAL			40	40	100.00
		TOTAL			523	532	98.31

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.46	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 5 failures:

Test rom_ctrl_sec_cm has 5 failures.

3.rom_ctrl_sec_cm.104463511901293070915739981216190750195603533259917822424766845940784054935680
Line 173, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 45683382ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 45683382ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
  Starting assertion attempts at time 45683382ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))

4.rom_ctrl_sec_cm.92676752322742282497003162301715913144211234749898906167568819427121534131006
Line 301, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 105507264ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 105507264ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
  Starting assertion attempts at time 105507264ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))

... and 3 more failures.

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'

has 3 failures:

Test rom_ctrl_sec_cm has 3 failures.

0.rom_ctrl_sec_cm.109105177147404778609822810199113789587266047351921392475223879993723742410122
Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 4694823ps failed at 4694823ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 4694823ps failed at 4694823ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

0.rom_ctrl_sec_cm.73742135651435345502071531691755604420542132509795905555930251503096708065547
Line 303, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 62771141ps failed at 62771141ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 62771141ps failed at 62771141ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

... and 1 more failures.

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 18.rom_ctrl_corrupt_sig_fatal_chk.60755762908420262986930026178419182442821780424363783820973744546618068990983
    Line 79, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 2842575045 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 2842575045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```