RV_TIMER Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: `c766185`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.090s	826.132us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.700s	62.598us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.650s	12.291us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.390s	354.222us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.750s	16.630us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.310s	142.255us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.650s	12.291us	20	20	100.00
		rv_timer_csr_aliasing	0.750s	16.630us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	9.100s	7904.688us	1	20	5.00
V2	disabled	rv_timer_disabled	3.830s	2908.905us	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	534.580s	3482687.884us	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	534.580s	3482687.884us	10	10	100.00
V2	stress	rv_timer_stress_all	8.540s	6973.814us	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.880s	15.500us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.650s	31.062us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.180s	699.082us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.180s	699.082us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.700s	62.598us	5	5	100.00
		rv_timer_csr_rw	0.650s	12.291us	20	20	100.00
		rv_timer_csr_aliasing	0.750s	16.630us	5	5	100.00
		rv_timer_same_csr_outstanding	0.910s	106.060us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.700s	62.598us	5	5	100.00
		rv_timer_csr_rw	0.650s	12.291us	20	20	100.00
		rv_timer_csr_aliasing	0.750s	16.630us	5	5	100.00
		rv_timer_same_csr_outstanding	0.910s	106.060us	20	20	100.00
V2		TOTAL			191	210	90.95
V2S	tl_intg_err	rv_timer_tl_intg_err	1.230s	155.631us	20	20	100.00
		rv_timer_sec_cm	1.190s	294.498us	5	5	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.230s	155.631us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.710s	224.562us	2	10	20.00
V3	max_value	rv_timer_max	1.110s	43.232us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	65.340s	88789.565us	14	20	70.00
V3		TOTAL			16	40	40.00
		TOTAL			307	350	87.71

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.22	100.00	100.00	100.00	--	100.00	96.82	98.53

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 27 failures:
- Test rv_timer_min has 8 failures.
  - 0.rv_timer_min.47992126078526716866896765006292947625204120750607103841932305260886533934217
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 118932637 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x81bb4d04) == 0x1
  UVM_INFO @ 118932637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_min.46179439978681294173512463639522169035931822354878489049843466375570289650743
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 237410848 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x77ab9504) == 0x1
  UVM_INFO @ 237410848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
- Test rv_timer_random_reset has 19 failures.
  - 0.rv_timer_random_reset.57427999769968709811199004882370010999995416796472448828822582489610738683461
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 128362284 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x75c80f04) == 0x1
  UVM_INFO @ 128362284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.90231440399573547152380658095376395073498167356182643308737070155541772115818
    Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 539432582 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5f4c104) == 0x1
  UVM_INFO @ 539432582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 10 failures:
- Test rv_timer_max has 10 failures.
  - 0.rv_timer_max.49640885788160012944302188698580335452474509258872121342830670518654604216010
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 236799046 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 236799046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.54077958333691317788437741424470845357490791179721237501599458200837307100652
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @  51911386 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  51911386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 4 failures:

Test rv_timer_stress_all_with_rand_reset has 4 failures.

14.rv_timer_stress_all_with_rand_reset.38536775034707427180898888508579085238714937221005203953808464901763483610424
Line 78, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/14.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 246521732 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 246521732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.rv_timer_stress_all_with_rand_reset.3867110325201325608408835791837324920156588562739951551065516470511349656580
Line 320, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/15.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10470661836 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10470661836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 1.rv_timer_stress_all_with_rand_reset.8016723169226829369349020517060478938345754275533954427339422415870590134517
    Line 218, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 67232229675 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 67232229675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 18.rv_timer_stress_all_with_rand_reset.97308473636876345949714637092984065377035889286889487173379602089265104245691
    Line 102, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/18.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1425950065 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 1425950065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```