SPI_DEVICE/1R1W Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: c766185

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	441.870s	141900.744us	100	100	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.740s	82.810us	10	10	100.00
V1	csr_rw	spi_device_csr_rw	3.050s	99.951us	40	40	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.140s	3847.339us	10	10	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.470s	910.232us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.400s	62.667us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.050s	99.951us	40	40	100.00
		spi_device_csr_aliasing	21.470s	910.232us	10	10	100.00
V1	mem_walk	spi_device_mem_walk	0.990s	12.102us	10	10	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.550s	311.443us	10	10	100.00
V1		TOTAL			230	230	100.00
V2	csb_read	spi_device_csb_read	1.200s	18.627us	100	100	100.00
V2	mem_parity	spi_device_mem_parity	1.430s	32.388us	20	40	50.00
V2	mem_cfg	spi_device_ram_cfg	1.070s	25.603us	1	2	50.00
V2	tpm_read	spi_device_tpm_rw	8.260s	311.239us	100	100	100.00
V2	tpm_write	spi_device_tpm_rw	8.260s	311.239us	100	100	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	29.940s	8406.300us	100	100	100.00
		spi_device_tpm_sts_read	1.380s	164.108us	100	100	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.190s	20989.895us	100	100	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	43.970s	24749.369us	100	100	100.00
		spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	40.000s	43250.375us	100	100	100.00
		spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	40.000s	43250.375us	100	100	100.00
		spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	cmd_info_slots	spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	cmd_read_status	spi_device_intercept	34.320s	4896.458us	100	100	100.00
		spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	cmd_read_jedec	spi_device_intercept	34.320s	4896.458us	100	100	100.00
		spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	cmd_read_sfdp	spi_device_intercept	34.320s	4896.458us	100	100	100.00
		spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	cmd_fast_read	spi_device_intercept	34.320s	4896.458us	100	100	100.00
		spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	cmd_read_pipeline	spi_device_intercept	34.320s	4896.458us	100	100	100.00
		spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	flash_cmd_upload	spi_device_upload	36.330s	24950.701us	100	100	100.00
V2	mailbox_command	spi_device_mailbox	100.890s	170207.882us	100	100	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	100.890s	170207.882us	100	100	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	100.890s	170207.882us	100	100	100.00
V2	cmd_read_buffer	spi_device_flash_mode	67.150s	5524.383us	100	100	100.00
		spi_device_read_buffer_direct	23.130s	1649.672us	99	100	99.00
V2	cmd_dummy_cycle	spi_device_mailbox	100.890s	170207.882us	100	100	100.00
		spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	quad_spi	spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	dual_spi	spi_device_flash_all	330.570s	206616.197us	100	100	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.970s	2239.957us	100	100	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.970s	2239.957us	100	100	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	441.870s	141900.744us	100	100	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	692.560s	385447.839us	100	100	100.00
V2	stress_all	spi_device_stress_all	981.490s	256916.537us	100	100	100.00
V2	alert_test	spi_device_alert_test	1.120s	15.232us	100	100	100.00
V2	intr_test	spi_device_intr_test	1.100s	19.238us	100	100	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.960s	318.050us	40	40	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.960s	318.050us	40	40	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.740s	82.810us	10	10	100.00
		spi_device_csr_rw	3.050s	99.951us	40	40	100.00
		spi_device_csr_aliasing	21.470s	910.232us	10	10	100.00
		spi_device_same_csr_outstanding	4.660s	160.148us	40	40	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.740s	82.810us	10	10	100.00
		spi_device_csr_rw	3.050s	99.951us	40	40	100.00
		spi_device_csr_aliasing	21.470s	910.232us	10	10	100.00
		spi_device_same_csr_outstanding	4.660s	160.148us	40	40	100.00
V2		TOTAL			1900	1922	98.86
V2S	tl_intg_err	spi_device_tl_intg_err	21.010s	3936.818us	40	40	100.00
		spi_device_sec_cm	1.580s	284.202us	10	10	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.010s	3936.818us	40	40	100.00
V2S		TOTAL			50	50	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	363.850s	283871.838us	99	100	99.00
		TOTAL			2279	2302	99.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.38	99.11	96.56	83.54	89.36	98.40	94.43	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.100959399459791376629407706900659430566866114597231539090048078214536968311323
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1176769 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[87])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1176769 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1176769 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[983])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.67574688837133267004392964227207942256773722531254030806143765971074876608192
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   8722408 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[65])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   8722408 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   8722408 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[961])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.intr_state reset value: * has 1 failures:

  • Test spi_device_read_buffer_direct has 1 failures.

    • 15.spi_device_read_buffer_direct.9872849379230005389736855680630061097073913720534890485714241110278841291425
      Line 73, in log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/15.spi_device_read_buffer_direct/latest/run.log

        UVM_ERROR @ 379923882 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: spi_device_reg_block.intr_state reset value: 0x0
        UVM_INFO @ 418723882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 44.spi_device_flash_mode_ignore_cmds.17948452702990170110067404577137161974426491910418132663139377085421286904507
      Line 110, in log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 42713783152 ps: (spi_device_pass_base_vseq.sv:705) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        UVM_INFO @ 44642058651 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 8/14
        UVM_INFO @ 44642058651 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 9/14
        UVM_INFO @ 51429951284 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 9/14
        UVM_INFO @ 51429951284 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 10/14
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.21358994657288043021391874879840075310389328570818780213176802128999119863813
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    932651 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc124cf [110000010010010011001111] vs 0x0 [0])
        UVM_ERROR @   1028651 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x26a057 [1001101010000001010111] vs 0x0 [0])
        UVM_ERROR @   1124651 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6cb644 [11011001011011001000100] vs 0x0 [0])
        UVM_ERROR @   1151651 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x272ebd [1001110010111010111101] vs 0x0 [0])
        UVM_ERROR @   1230651 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7ae670 [11110101110011001110000] vs 0x0 [0])