SPI_HOST Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: c766185

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	99.000s	11079.063us	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	19.121us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	60.113us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	127.414us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	22.487us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	585.685us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	60.113us	20	20	100.00
		spi_host_csr_aliasing	2.000s	22.487us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	16.517us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	62.076us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	2.000s	34.422us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	27.000s	1998.224us	50	50	100.00
		spi_host_error_cmd	2.000s	59.852us	50	50	100.00
		spi_host_event	818.000s	114102.882us	50	50	100.00
V2	clock_rate	spi_host_speed	8.000s	168.075us	50	50	100.00
V2	speed	spi_host_speed	8.000s	168.075us	50	50	100.00
V2	chip_select_timing	spi_host_speed	8.000s	168.075us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	482.000s	63153.972us	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	67.352us	50	50	100.00
V2	cpol_cpha	spi_host_speed	8.000s	168.075us	50	50	100.00
V2	full_cycle	spi_host_speed	8.000s	168.075us	50	50	100.00
V2	duplex	spi_host_smoke	99.000s	11079.063us	50	50	100.00
V2	tx_rx_only	spi_host_smoke	99.000s	11079.063us	50	50	100.00
V2	stress_all	spi_host_stress_all	160.000s	28786.492us	50	50	100.00
V2	spien	spi_host_spien	20.000s	2653.256us	49	50	98.00
V2	stall	spi_host_status_stall	1778.000s	159375.707us	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	23.000s	2052.681us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	27.000s	1998.224us	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	18.739us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	23.467us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	206.179us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	206.179us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	19.121us	5	5	100.00
		spi_host_csr_rw	2.000s	60.113us	20	20	100.00
		spi_host_csr_aliasing	2.000s	22.487us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	130.932us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	19.121us	5	5	100.00
		spi_host_csr_rw	2.000s	60.113us	20	20	100.00
		spi_host_csr_aliasing	2.000s	22.487us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	130.932us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_sec_cm	2.000s	67.564us	5	5	100.00
		spi_host_tl_intg_err	3.000s	233.301us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	233.301us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	357.000s	10020.190us	10	10	100.00
		TOTAL			838	840	99.76

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.19	96.87	93.45	98.69	94.35	88.02	100.00	95.21	90.42

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 21.spi_host_status_stall.54186241760645915297511798993984873319294787684255040192375254318792899246612
      Line 845, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/21.spi_host_status_stall/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 452088897 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
        UVM_ERROR @ 452088897 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=452089000 ps
        UVM_INFO @ 452088897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_spien has 1 failures.

    • 46.spi_host_spien.94927440940910824667590590151494660766365343619600663084547206222505515764130
      Line 327, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/46.spi_host_spien/latest/run.log

        UVM_FATAL @ 12648785871 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x7a21bf54, Comparison=CompareOpEq, exp_data=0x0, call_count=48
        UVM_INFO @ 12648785871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---