SRAM_CTRL/RET Simulation Results

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: `c766185`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	103.860s	2914.226us	100	100	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.810s	24.770us	10	10	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.080s	42.824us	40	40	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.810s	1876.543us	10	10	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.820s	63.803us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.350s	1380.030us	38	40	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.080s	42.824us	40	40	100.00
		sram_ctrl_csr_aliasing	0.820s	63.803us	10	10	100.00
V1	mem_walk	sram_ctrl_mem_walk	378.920s	93967.734us	100	100	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	215.340s	115702.832us	100	100	100.00
V1		TOTAL			408	410	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	1864.520s	47329.652us	100	100	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	453.580s	43839.684us	100	100	100.00
V2	bijection	sram_ctrl_bijection	2550.120s	172282.243us	100	100	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1714.630s	19970.182us	100	100	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	152.540s	73690.215us	100	100	100.00
V2	executable	sram_ctrl_executable	1699.790s	433223.180us	100	100	100.00
V2	partial_access	sram_ctrl_partial_access	120.220s	1144.351us	100	100	100.00
		sram_ctrl_partial_access_b2b	597.950s	28870.484us	100	100	100.00
V2	max_throughput	sram_ctrl_max_throughput	121.660s	1572.359us	100	100	100.00
		sram_ctrl_throughput_w_partial_write	115.420s	787.420us	100	100	100.00
		sram_ctrl_throughput_w_readback	120.630s	919.314us	100	100	100.00
V2	regwen	sram_ctrl_regwen	1260.240s	15679.737us	100	100	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.790s	4801.746us	100	100	100.00
V2	stress_all	sram_ctrl_stress_all	7624.200s	1580038.045us	100	100	100.00
V2	alert_test	sram_ctrl_alert_test	1.040s	43.582us	100	100	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.060s	826.418us	40	40	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.060s	826.418us	40	40	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.810s	24.770us	10	10	100.00
		sram_ctrl_csr_rw	1.080s	42.824us	40	40	100.00
		sram_ctrl_csr_aliasing	0.820s	63.803us	10	10	100.00
		sram_ctrl_same_csr_outstanding	1.100s	63.736us	40	40	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.810s	24.770us	10	10	100.00
		sram_ctrl_csr_rw	1.080s	42.824us	40	40	100.00
		sram_ctrl_csr_aliasing	0.820s	63.803us	10	10	100.00
		sram_ctrl_same_csr_outstanding	1.100s	63.736us	40	40	100.00
V2		TOTAL			1580	1580	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	60.380s	100569.363us	40	40	100.00
V2S	tl_intg_err	sram_ctrl_tl_intg_err	2.550s	2370.764us	40	40	100.00
		sram_ctrl_sec_cm	1.030s	12.147us	0	10	0.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.030s	12.147us	0	10	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.550s	2370.764us	40	40	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1260.240s	15679.737us	100	100	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1260.240s	15679.737us	100	100	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.080s	42.824us	40	40	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1699.790s	433223.180us	100	100	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1699.790s	433223.180us	100	100	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1699.790s	433223.180us	100	100	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	152.540s	73690.215us	100	100	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	11.510s	6022.114us	89	100	89.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	60.380s	100569.363us	40	40	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.760s	10969.720us	68	100	68.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	103.860s	2914.226us	100	100	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	103.860s	2914.226us	100	100	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1699.790s	433223.180us	100	100	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.030s	12.147us	0	10	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	152.540s	73690.215us	100	100	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.030s	12.147us	0	10	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.030s	12.147us	0	10	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	103.860s	2914.226us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.030s	12.147us	0	10	0.00
V2S		TOTAL			237	290	81.72
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	868.690s	11370.873us	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			2325	2380	97.69

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.42	99.07	92.90	90.66	100.00	97.98	95.79	98.52

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 31 failures:
- Test sram_ctrl_readback_err has 31 failures.
  - 0.sram_ctrl_readback_err.63018540596739790050857888767874545904431957668051890619038830545582761542313
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  99494453 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7d) != exp (0x79)
  UVM_INFO @  99494453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.sram_ctrl_readback_err.31070558857780387090115801524653771291205272359632354425021855106580339851667
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  49030816 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x13) != exp (0x2e)
  UVM_INFO @  49030816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 29 more failures.
Offending 'reqfifo_rvalid' has 11 failures:
- Test sram_ctrl_mubi_enc_err has 11 failures.
  - 5.sram_ctrl_mubi_enc_err.26545761127684728471389201342130826523721156781171684494169716508412855396097
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  28595775 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  28595775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 17.sram_ctrl_mubi_enc_err.72144245746757740767007171006384021995768641867350287392855694296945734041490
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  48964016 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  48964016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 7 failures:
- Test sram_ctrl_sec_cm has 7 failures.
  - 3.sram_ctrl_sec_cm.103242471943804614003354512099107449618472013194242950409915772236476622197547
    Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   8247877 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   8247877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.sram_ctrl_sec_cm.94039810475781368914700726659932490012005693285209355345063530662689668429412
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   2990421 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   2990421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

Offending '(depth_o <= *'(Depth))' has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

0.sram_ctrl_sec_cm.41560054942606998267877619222281298675914045384331485687581998548338432935712
Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @  12146702 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @  12146702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.sram_ctrl_sec_cm.108030849594347351712129028410479571609303770373821264521453885906638344854450
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @   1075253 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @   1075253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.83268636423644057519495671473834194593740440855520082194825633643162284983795
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  25081723 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @  25081723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.57953876609419571238126686261774945406802057460535014395372883885577847891833
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  24700904 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (15 [0xf] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  24700904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 2.sram_ctrl_sec_cm.109016486705358581893723746394814206435572765418424898168573904406603293821361
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   2824187 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2824187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5402) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_readback_err has 1 failures.

19.sram_ctrl_readback_err.40895632452215092069977652884964659332932155703090044057058410754171481925835
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/19.sram_ctrl_readback_err/latest/run.log

  UVM_ERROR @ 233369087 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5402) { a_addr: 'hbc58349c  a_data: 'h85  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4b  a_opcode: 'h1  a_user: 'h27e1e  d_param: 'h0  d_source: 'h4b  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 233369087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---