c766185| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 8.750s | 2110.460us | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 10.140s | 2460.200us | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 5.580s | 2391.521us | 5 | 5 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 6.510s | 2516.187us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 12.530s | 6052.488us | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 8.670s | 2035.015us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 284.660s | 60759.353us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 13.210s | 2711.500us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 6.390s | 2064.900us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 8.670s | 2035.015us | 20 | 20 | 100.00 |
| sysrst_ctrl_csr_aliasing | 13.210s | 2711.500us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 165 | 165 | 100.00 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 452.560s | 185967.493us | 50 | 50 | 100.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 387.170s | 156903.179us | 92 | 100 | 92.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 398.350s | 328539.649us | 50 | 50 | 100.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 513.110s | 1111083.349us | 48 | 50 | 96.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 10.330s | 2510.281us | 50 | 50 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 8.890s | 2093.806us | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 2837.310s | 975409.324us | 50 | 50 | 100.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 10.940s | 2612.252us | 50 | 50 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 716.010s | 3197101.708us | 41 | 50 | 82.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 21.390s | 41219.795us | 2 | 2 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 1071.740s | 432169.389us | 48 | 50 | 96.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 8.460s | 2008.587us | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 7.750s | 2015.924us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 9.620s | 2131.285us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 9.620s | 2131.285us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 12.530s | 6052.488us | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 8.670s | 2035.015us | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 13.210s | 2711.500us | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 29.790s | 10046.962us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 12.530s | 6052.488us | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 8.670s | 2035.015us | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 13.210s | 2711.500us | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 29.790s | 10046.962us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 671 | 692 | 96.97 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 94.950s | 42012.515us | 5 | 5 | 100.00 |
| sysrst_ctrl_tl_intg_err | 102.800s | 42392.775us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 102.800s | 42392.775us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 25.420s | 13791.475us | 46 | 50 | 92.00 |
| V3 | TOTAL | 46 | 50 | 92.00 | |||
| TOTAL | 907 | 932 | 97.32 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.01 | 98.96 | 97.93 | 100.00 | 93.59 | 99.04 | 98.37 | 84.18 |
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 8 failures:
Test sysrst_ctrl_ultra_low_pwr has 5 failures.
0.sysrst_ctrl_ultra_low_pwr.89567623992281721441721312906904098072221672957557711987481090708228106839034
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2487350146 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 2494850146 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_INFO @ 570274850146 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 570288531640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.sysrst_ctrl_ultra_low_pwr.87242086012528806066488593906030865357685063078603594369573775231064424708364
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2529138967 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 95551638967 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_ERROR @ 164204138967 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 164204138967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.
8.sysrst_ctrl_stress_all_with_rand_reset.49765501834815619818554254494841899569619085040321373715532085530223714041608
Line 391, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4271454893 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 4313954893 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_ERROR @ 7231504664 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 7231504664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.sysrst_ctrl_stress_all_with_rand_reset.22418469056592285624724848435632695837933970120895748614625248766941304254867
Line 397, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11900998044 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 11938498044 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 13133498044 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 13196857442 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq
UVM_INFO @ 15193712588 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:23) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Starting the body from flash_wr_prot_vseq
Test sysrst_ctrl_stress_all has 1 failures.
35.sysrst_ctrl_stress_all.91632711091716415548586020210523817446084256896414050766217410168031923557955
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 656802803589 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 1635960303589 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1635960303589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 6 failures:
Test sysrst_ctrl_ultra_low_pwr has 3 failures.
24.sysrst_ctrl_ultra_low_pwr.2907558849896306639733140017216988490249798405490777283937891644911433793097
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 5725216477 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 5725236476 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 5725236476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.sysrst_ctrl_ultra_low_pwr.87470602286340959516060266047540290189002831197944015413778620233322617563846
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 5475027336 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 5475040839 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 5475040839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test sysrst_ctrl_edge_detect has 2 failures.
43.sysrst_ctrl_edge_detect.1061241216491693594561300737462643008509322094261329838544972942341326829449
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest/run.log
UVM_ERROR @ 2623890724 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 2623964797 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2623964797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.sysrst_ctrl_edge_detect.40177862014231195660487012747920641671263958867596583382477048006029657893994
Line 384, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest/run.log
UVM_ERROR @ 2523841301 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 2523862352 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2523862352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_stress_all has 1 failures.
47.sysrst_ctrl_stress_all.64642193884834302918875943710883426493710667595529967266623299035295039570434
Line 383, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 5847915647 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 5847956462 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 5847956462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 3 failures:
39.sysrst_ctrl_combo_detect_with_pre_cond.7681662199655161689300969203072665171120562551897139493210762752501979535216
Line 402, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 38197892171 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 38197892171 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 38197892171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
61.sysrst_ctrl_combo_detect_with_pre_cond.85198260659308717325494209136863898264922548960073864804430003780944187199995
Line 421, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 51515044016 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 51515044016 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 51515044016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 2 failures:
19.sysrst_ctrl_combo_detect_with_pre_cond.27720308457669813893681209318292693063606397547710034576120863823508480111160
Line 412, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 36075804214 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 36205804214 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 36225804214 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 46376231493 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2f
UVM_INFO @ 46376251695 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x25
23.sysrst_ctrl_combo_detect_with_pre_cond.88047108054565446306023000121209381917348976122707607166672815414212310137559
Line 461, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 77137991614 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 77242991614 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 77262991614 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 87454694994 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x32
UVM_INFO @ 87454725921 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xf
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 2 failures:
38.sysrst_ctrl_combo_detect_with_pre_cond.48597051029603224237032886985493065713554186246324302850389113066591736283984
Line 420, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 43269494772 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 43499656574 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8])
UVM_INFO @ 43499656574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
76.sysrst_ctrl_combo_detect_with_pre_cond.34599274872631548081632722974681940776262952301949846636924860982586177755395
Line 392, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 13260996585 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 13310996585 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 13330996585 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_ERROR @ 13411127587 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 1 [0x1])
UVM_INFO @ 13411127587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:
16.sysrst_ctrl_stress_all_with_rand_reset.38270916624678116303989507288597072600530756701879212913050448457165982150020
Line 406, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7513242372 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7516735217 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
Stress w/ reset is done for run 4/5
UVM_INFO @ 7520671752 ps: (cip_base_vseq.sv:1097) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 5/5
UVM_INFO @ 7520671752 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/692
UVM_FATAL (cip_base_vseq.sv:885) [sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred! has 1 failures:
23.sysrst_ctrl_ultra_low_pwr.50085072912299349463806791448658319843958654639502557413338578849100451575279
Line 384, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_FATAL @ 1102398286172 ps: (cip_base_vseq.sv:885) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred!
UVM_INFO @ 1102398286172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-* has 1 failures:
25.sysrst_ctrl_combo_detect_with_pre_cond.112585272619350029256989720592542459672753529470013775025313195993864598355439
Line 391, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 14610090125 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4
UVM_ERROR @ 14610090125 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4
UVM_INFO @ 14610090125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:124) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at Key0Idx has 1 failures:
45.sysrst_ctrl_stress_all_with_rand_reset.1484327096424768695892669223141136481486299418634879121508358138086345755195
Line 453, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19496417701 ps: (sysrst_ctrl_edge_detect_vseq.sv:124) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key0Idx
UVM_ERROR @ 19496417701 ps: (sysrst_ctrl_edge_detect_vseq.sv:124) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
UVM_INFO @ 19496417701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---