ADC_CTRL Simulation Results

Sunday December 07 2025 00:12:41 UTC

GitHub Revision: `9ce72b8`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	22.470s	5988.449us	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.570s	1090.455us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.780s	346.477us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	39.850s	43611.649us	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.480s	1168.091us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.980s	383.924us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.780s	346.477us	20	20	100.00
		adc_ctrl_csr_aliasing	3.480s	1168.091us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	1362.670s	493156.985us	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1231.000s	507007.836us	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	1146.630s	493141.960us	48	50	96.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1218.920s	495662.671us	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	1178.420s	544584.092us	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1366.730s	584064.587us	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	1235.990s	549670.803us	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	1205.900s	613327.333us	38	50	76.00
V2	poweron_counter	adc_ctrl_poweron_counter	18.190s	5113.838us	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	147.960s	45587.254us	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	406.350s	134214.073us	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	7218.360s	3666428.894us	45	50	90.00
V2	alert_test	adc_ctrl_alert_test	2.480s	491.241us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.700s	429.009us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.740s	589.619us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.740s	589.619us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.570s	1090.455us	5	5	100.00
		adc_ctrl_csr_rw	1.780s	346.477us	20	20	100.00
		adc_ctrl_csr_aliasing	3.480s	1168.091us	5	5	100.00
		adc_ctrl_same_csr_outstanding	9.520s	2365.368us	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.570s	1090.455us	5	5	100.00
		adc_ctrl_csr_rw	1.780s	346.477us	20	20	100.00
		adc_ctrl_csr_aliasing	3.480s	1168.091us	5	5	100.00
		adc_ctrl_same_csr_outstanding	9.520s	2365.368us	20	20	100.00
V2		TOTAL			720	740	97.30
V2S	tl_intg_err	adc_ctrl_tl_intg_err	20.370s	8463.153us	20	20	100.00
		adc_ctrl_sec_cm	17.480s	8110.873us	5	5	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.370s	8463.153us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	226.220s	10000000.000us	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			898	920	97.61

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	99.05	96.03	100.00	100.00	98.64	95.95	92.03

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 10 failures:

Test adc_ctrl_clock_gating has 7 failures.

4.adc_ctrl_clock_gating.184808310929664468806517600374329889542508670429812542517407438969910374022
Line 318, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 3223738425 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 3223738425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.adc_ctrl_clock_gating.47362196042825072513576447893601622508443918291725249597945335952084686189164
Line 318, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 4340655737 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 4340655737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test adc_ctrl_stress_all has 2 failures.

37.adc_ctrl_stress_all.23108140485430870219880939466403093155351072977098404114429543117311951245188
Line 416, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 43115499704 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 43115499704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.adc_ctrl_stress_all.31260256678626968222095166020415488664596241283596715109364782859611361304972
Line 337, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 169705893496 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 169705893496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
- 47.adc_ctrl_stress_all_with_rand_reset.59385429702386330375723498353421330986443477470963322719465186169119400332128
  Line 328, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3060878143 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 3060878143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 8 failures:
- Test adc_ctrl_clock_gating has 5 failures.
  - 7.adc_ctrl_clock_gating.2272110334785788579384858195312591226265827808763931886418651375159718695042
    Line 318, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.adc_ctrl_clock_gating.77891787632060635566378810736176580632623078303524083516032830222264122164348
    Line 335, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
- Test adc_ctrl_stress_all has 2 failures.
  - 24.adc_ctrl_stress_all.39883321063078050472374907891097379041819169983385053088682409785576934805225
    Line 319, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 29.adc_ctrl_stress_all.988810285867509178993634549866783490394201570949446064244432399617871553167
    Line 319, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 36.adc_ctrl_stress_all_with_rand_reset.73491638009311882679978963506286276076698741941920915089534449135999146221420
    Line 381, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 4 failures:

Test adc_ctrl_filters_interrupt has 2 failures.

19.adc_ctrl_filters_interrupt.105931178859897587112014661226571249295164127249508283954221570843743605104335
Line 334, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 329350931280 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 329350931280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.adc_ctrl_filters_interrupt.64498134783610561185173529151027821931176789718024841283915841045909186149876
Line 318, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 81427167152 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 81427167152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 1 failures.

23.adc_ctrl_stress_all.17829479214461792070663519515978894358821855543544387644720918650007013172446
Line 409, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 368489113615 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 368489113615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_both has 1 failures.

41.adc_ctrl_filters_both.62478588961142541821648846049352847176004263249981933690606253686892362213149
Line 318, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 165675165843 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 165675165843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---