AES/MASKED Simulation Results

Sunday December 07 2025 00:12:41 UTC

GitHub Revision: `9ce72b8`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	76.899us	2	2	100.00
V1	smoke	aes_smoke	8.000s	133.215us	100	100	100.00
V1	csr_hw_reset	aes_csr_hw_reset	25.000s	72.457us	10	10	100.00
V1	csr_rw	aes_csr_rw	25.000s	95.470us	40	40	100.00
V1	csr_bit_bash	aes_csr_bit_bash	29.000s	338.324us	10	10	100.00
V1	csr_aliasing	aes_csr_aliasing	26.000s	378.869us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	26.000s	113.113us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	25.000s	95.470us	40	40	100.00
		aes_csr_aliasing	26.000s	378.869us	10	10	100.00
V1		TOTAL			212	212	100.00
V2	algorithm	aes_smoke	8.000s	133.215us	100	100	100.00
		aes_config_error	11.000s	500.240us	100	100	100.00
		aes_stress	11.000s	1436.783us	100	100	100.00
V2	key_length	aes_smoke	8.000s	133.215us	100	100	100.00
		aes_config_error	11.000s	500.240us	100	100	100.00
		aes_stress	11.000s	1436.783us	100	100	100.00
V2	back2back	aes_stress	11.000s	1436.783us	100	100	100.00
		aes_b2b	25.000s	1061.998us	100	100	100.00
V2	backpressure	aes_stress	11.000s	1436.783us	100	100	100.00
V2	multi_message	aes_smoke	8.000s	133.215us	100	100	100.00
		aes_config_error	11.000s	500.240us	100	100	100.00
		aes_stress	11.000s	1436.783us	100	100	100.00
		aes_alert_reset	8.000s	175.357us	100	100	100.00
V2	failure_test	aes_man_cfg_err	5.000s	231.002us	100	100	100.00
		aes_config_error	11.000s	500.240us	100	100	100.00
		aes_alert_reset	8.000s	175.357us	100	100	100.00
V2	trigger_clear_test	aes_clear	14.000s	704.486us	100	100	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	452.345us	2	2	100.00
V2	reset_recovery	aes_alert_reset	8.000s	175.357us	100	100	100.00
V2	stress	aes_stress	11.000s	1436.783us	100	100	100.00
V2	sideload	aes_stress	11.000s	1436.783us	100	100	100.00
		aes_sideload	7.000s	494.880us	100	100	100.00
V2	deinitialization	aes_deinit	26.000s	1498.386us	100	100	100.00
V2	stress_all	aes_stress_all	58.000s	1268.957us	19	20	95.00
V2	alert_test	aes_alert_test	3.000s	241.251us	100	100	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	27.000s	129.845us	40	40	100.00
V2	tl_d_illegal_access	aes_tl_errors	27.000s	129.845us	40	40	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	25.000s	72.457us	10	10	100.00
		aes_csr_rw	25.000s	95.470us	40	40	100.00
		aes_csr_aliasing	26.000s	378.869us	10	10	100.00
		aes_same_csr_outstanding	26.000s	76.702us	40	40	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	25.000s	72.457us	10	10	100.00
		aes_csr_rw	25.000s	95.470us	40	40	100.00
		aes_csr_aliasing	26.000s	378.869us	10	10	100.00
		aes_same_csr_outstanding	26.000s	76.702us	40	40	100.00
V2		TOTAL			1001	1002	99.90
V2S	reseeding	aes_reseed	25.000s	1672.215us	100	100	100.00
V2S	fault_inject	aes_fi	16.000s	2716.209us	97	100	97.00
		aes_control_fi	58.000s	10068.255us	569	600	94.83
		aes_cipher_fi	55.000s	10004.694us	664	700	94.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	26.000s	77.608us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	26.000s	77.608us	40	40	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	26.000s	77.608us	40	40	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	26.000s	77.608us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	26.000s	298.611us	40	40	100.00
V2S	tl_intg_err	aes_tl_intg_err	26.000s	148.245us	40	40	100.00
		aes_sec_cm	15.000s	2436.129us	10	10	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	26.000s	148.245us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	175.357us	100	100	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	26.000s	77.608us	40	40	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	133.215us	100	100	100.00
		aes_stress	11.000s	1436.783us	100	100	100.00
		aes_alert_reset	8.000s	175.357us	100	100	100.00
		aes_core_fi	244.000s	10008.307us	134	140	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	26.000s	77.608us	40	40	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	65.048us	100	100	100.00
		aes_stress	11.000s	1436.783us	100	100	100.00
V2S	sec_cm_key_sideload	aes_stress	11.000s	1436.783us	100	100	100.00
		aes_sideload	7.000s	494.880us	100	100	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	65.048us	100	100	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	65.048us	100	100	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	65.048us	100	100	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	65.048us	100	100	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	65.048us	100	100	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	11.000s	1436.783us	100	100	100.00
V2S	sec_cm_key_masking	aes_stress	11.000s	1436.783us	100	100	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.000s	2716.209us	97	100	97.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.000s	2716.209us	97	100	97.00
		aes_control_fi	58.000s	10068.255us	569	600	94.83
		aes_cipher_fi	55.000s	10004.694us	664	700	94.86
		aes_ctr_fi	3.000s	78.306us	99	100	99.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.000s	2716.209us	97	100	97.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.000s	2716.209us	97	100	97.00
		aes_control_fi	58.000s	10068.255us	569	600	94.83
		aes_cipher_fi	55.000s	10004.694us	664	700	94.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	55.000s	10004.694us	664	700	94.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.000s	2716.209us	97	100	97.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.000s	2716.209us	97	100	97.00
		aes_control_fi	58.000s	10068.255us	569	600	94.83
		aes_ctr_fi	3.000s	78.306us	99	100	99.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.000s	2716.209us	97	100	97.00
		aes_control_fi	58.000s	10068.255us	569	600	94.83
		aes_cipher_fi	55.000s	10004.694us	664	700	94.86
		aes_ctr_fi	3.000s	78.306us	99	100	99.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	175.357us	100	100	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.000s	2716.209us	97	100	97.00
		aes_control_fi	58.000s	10068.255us	569	600	94.83
		aes_cipher_fi	55.000s	10004.694us	664	700	94.86
		aes_ctr_fi	3.000s	78.306us	99	100	99.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.000s	2716.209us	97	100	97.00
		aes_control_fi	58.000s	10068.255us	569	600	94.83
		aes_cipher_fi	55.000s	10004.694us	664	700	94.86
		aes_ctr_fi	3.000s	78.306us	99	100	99.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.000s	2716.209us	97	100	97.00
		aes_control_fi	58.000s	10068.255us	569	600	94.83
		aes_ctr_fi	3.000s	78.306us	99	100	99.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.000s	2716.209us	97	100	97.00
		aes_control_fi	58.000s	10068.255us	569	600	94.83
		aes_cipher_fi	55.000s	10004.694us	664	700	94.86
V2S		TOTAL			1893	1970	96.09
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	49.000s	6286.387us	0	20	0.00
V3		TOTAL			0	20	0.00
		TOTAL			3106	3204	96.94

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.61	96.47	99.42	95.34	98.07	97.04	98.36	98.79

Failure Buckets

Job timed out after * minutes has 32 failures:
- Test aes_ctr_fi has 1 failures.
  - 25.aes_ctr_fi.19336087863878305793885246855219026999689386746139216608469435864844696801564
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/25.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_control_fi has 13 failures.
  - 26.aes_control_fi.16038388812467838141927160574235363900055014763497992556495038169179015388087
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 54.aes_control_fi.92964386898590169625143961884838440315121196836488738953941111584537090354812
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 18 failures.
  - 55.aes_cipher_fi.105699385544101668822526258185522315150817934641397030057823652054347410551308
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/55.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 59.aes_cipher_fi.25009493644851125212012656298237509514203429722814168251513248954792263764553
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 16 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 18 failures:
- Test aes_control_fi has 18 failures.
  - 4.aes_control_fi.51363909964601504908889385232838867734198305810236830989789545550426858105964
    Line 132, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016208832 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016208832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 35.aes_control_fi.34389507548221274486863483295923566326488273313774607129051919378547265458578
    Line 148, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010593356 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010593356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 18 failures:
- Test aes_cipher_fi has 18 failures.
  - 30.aes_cipher_fi.5024992987994534655820027558285845645941505457044441692387287572070744379257
    Line 146, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007261555 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007261555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 39.aes_cipher_fi.41896334195496060916394668760011453561096877490545847970070931315884231590104
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/39.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007965580 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007965580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 14 failures:

Test aes_stress_all_with_rand_reset has 14 failures.

0.aes_stress_all_with_rand_reset.75360076582184018813797245600348679563624118553737073726323567945751110501311
Line 884, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2171546127 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2171546127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.112794244986942985247026867267247144373541081919348550665428660147012930949411
Line 978, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2168031991 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2168031991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 4.aes_stress_all_with_rand_reset.52076356760379714078518706734416535240417646193115917494274459095975488337312
    Line 539, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1374626734 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1374626734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.aes_stress_all_with_rand_reset.62196932491253148079950650726518237049387417845045120694917305476192299685497
    Line 317, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2766808807 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2766808807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 3 failures:

Test aes_fi has 3 failures.

8.aes_fi.30223041431993350897813876606335115154461205041079518525575624722522535081054
Line 5721, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_fi/latest/run.log

  UVM_FATAL @ 194219487 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 194219487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.aes_fi.46881275102590021992096086568281352677933589397548854991937181752700195043268
Line 7936, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/31.aes_fi/latest/run.log

  UVM_FATAL @  42233007 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  42233007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 58.aes_core_fi.95083804354846474193263364102862655638288406208147567520277523028334823260552
    Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/58.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002956687 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002956687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 17.aes_core_fi.79947278722320520348481115876901748283071203584178829489560645258681934758900
    Line 145, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/17.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10037857304 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037857304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.1803009255035207455551284967686175878795382353473846157449763791878893859989
    Line 333, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 252079673 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 252079673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 10.aes_core_fi.36076526927931464577027455206037624774810257544406088841490690299970726506551
    Line 132, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10030310733 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xb18d1684, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10030310733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 11.aes_core_fi.48578396798212388497903964476119445556151002251040401442279012034878531809054
    Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008307255 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x9b3c0a84, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10008307255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 68.aes_core_fi.50955939207326913965705629389383033485874944293793403871744983319095849174611
    Line 142, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/68.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10046902431 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xb7bdb784, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10046902431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.72715195719710247765111271160401414825649952865703415480269480979923180377490
    Line 1612, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6286386804 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 6286386804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

9.aes_stress_all.36614833291318769430474146116924082084736326906858855552278134151095309086517
Line 168987, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 1177396885 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 1177371244 PS)
  UVM_ERROR @ 1177396885 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 1177396885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.41386966643640316869817678459746059912882485899310070828695582270171001651341
    Line 180, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  44247207 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  44247207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```