CSRNG Simulation Results

Sunday December 07 2025 00:12:41 UTC

GitHub Revision: 9ce72b8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	191.263us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	2.000s	29.328us	5	5	100.00
V1	csr_rw	csrng_csr_rw	3.000s	63.875us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	10.000s	443.269us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	282.454us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	182.736us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	3.000s	63.875us	20	20	100.00
		csrng_csr_aliasing	6.000s	282.454us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	18.000s	1212.468us	200	200	100.00
V2	alerts	csrng_alert	54.000s	5197.689us	500	500	100.00
V2	err	csrng_err	4.000s	138.150us	500	500	100.00
V2	cmds	csrng_cmds	381.000s	18465.191us	50	50	100.00
V2	life cycle	csrng_cmds	381.000s	18465.191us	50	50	100.00
V2	stress_all	csrng_stress_all	1456.000s	122728.770us	48	50	96.00
V2	intr_test	csrng_intr_test	3.000s	82.966us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	226.541us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	10.000s	641.292us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	10.000s	641.292us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	2.000s	29.328us	5	5	100.00
		csrng_csr_rw	3.000s	63.875us	20	20	100.00
		csrng_csr_aliasing	6.000s	282.454us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	639.353us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	2.000s	29.328us	5	5	100.00
		csrng_csr_rw	3.000s	63.875us	20	20	100.00
		csrng_csr_aliasing	6.000s	282.454us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	639.353us	20	20	100.00
V2		TOTAL			1438	1440	99.86
V2S	tl_intg_err	csrng_tl_intg_err	16.000s	551.260us	20	20	100.00
		csrng_sec_cm	10.000s	264.777us	5	5	100.00
V2S	sec_cm_config_regwen	csrng_csr_rw	3.000s	63.875us	20	20	100.00
		csrng_regwen	3.000s	60.971us	50	50	100.00
V2S	sec_cm_config_mubi	csrng_alert	54.000s	5197.689us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	1456.000s	122728.770us	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
		csrng_sec_cm	10.000s	264.777us	5	5	100.00
V2S	sec_cm_cmd_stage_fsm_sparse	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
		csrng_sec_cm	10.000s	264.777us	5	5	100.00
V2S	sec_cm_ctr_drbg_fsm_sparse	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
		csrng_sec_cm	10.000s	264.777us	5	5	100.00
V2S	sec_cm_ctr_drbg_ctr_redun	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
		csrng_sec_cm	10.000s	264.777us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
		csrng_sec_cm	10.000s	264.777us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	54.000s	5197.689us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	1456.000s	122728.770us	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	54.000s	5197.689us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	16.000s	551.260us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
		csrng_sec_cm	10.000s	264.777us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
		csrng_sec_cm	10.000s	264.777us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	18.000s	1212.468us	200	200	100.00
		csrng_err	4.000s	138.150us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	270.000s	24852.408us	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1628	1630	99.88

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.65	98.72	96.79	99.61	96.80	93.64	95.24	95.85	91.32

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
  • Test csrng_stress_all has 2 failures.

    • 28.csrng_stress_all.5322040691225351454068483756491850646429976441581843373495220999997132070982
      Line 179, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/28.csrng_stress_all/latest/run.log

        UVM_ERROR @ 16363819587 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 16363819587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 48.csrng_stress_all.46021578803822380856291807454709117511408294233962193625974876195433907150217
      Line 145, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/48.csrng_stress_all/latest/run.log

        UVM_ERROR @ 143713239 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 143713239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---