EDN/EDN1 Simulation Results

Sunday December 07 2025 00:12:41 UTC

GitHub Revision: 9ce72b8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.000s	0.000us	0	100	0.00
V1	csr_hw_reset	edn_csr_hw_reset	0.000s	0.000us	0	10	0.00
V1	csr_rw	edn_csr_rw	0.000s	0.000us	0	40	0.00
V1	csr_bit_bash	edn_csr_bit_bash	0.000s	0.000us	0	10	0.00
V1	csr_aliasing	edn_csr_aliasing	0.000s	0.000us	0	10	0.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.000s	0.000us	0	40	0.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.000s	0.000us	0	40	0.00
		edn_csr_aliasing	0.000s	0.000us	0	10	0.00
V1		TOTAL			0	210	0.00
V2	firmware	edn_genbits	0.000s	0.000us	0	600	0.00
V2	csrng_commands	edn_genbits	0.000s	0.000us	0	600	0.00
V2	genbits	edn_genbits	0.000s	0.000us	0	600	0.00
V2	interrupts	edn_intr	0.000s	0.000us	0	100	0.00
V2	alerts	edn_alert	0.000s	0.000us	0	400	0.00
V2	errs	edn_err	0.000s	0.000us	0	200	0.00
V2	disable	edn_disable	0.000s	0.000us	0	100	0.00
		edn_disable_auto_req_mode	0.000s	0.000us	0	100	0.00
V2	stress_all	edn_stress_all	0.000s	0.000us	0	100	0.00
V2	intr_test	edn_intr_test	0.000s	0.000us	0	100	0.00
V2	alert_test	edn_alert_test	0.000s	0.000us	0	100	0.00
V2	tl_d_oob_addr_access	edn_tl_errors	0.000s	0.000us	0	40	0.00
V2	tl_d_illegal_access	edn_tl_errors	0.000s	0.000us	0	40	0.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.000s	0.000us	0	10	0.00
		edn_csr_rw	0.000s	0.000us	0	40	0.00
		edn_csr_aliasing	0.000s	0.000us	0	10	0.00
		edn_same_csr_outstanding	0.000s	0.000us	0	40	0.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.000s	0.000us	0	10	0.00
		edn_csr_rw	0.000s	0.000us	0	40	0.00
		edn_csr_aliasing	0.000s	0.000us	0	10	0.00
		edn_same_csr_outstanding	0.000s	0.000us	0	40	0.00
V2		TOTAL			0	1880	0.00
V2S	tl_intg_err	edn_sec_cm	0.000s	0.000us	0	10	0.00
		edn_tl_intg_err	0.000s	0.000us	0	40	0.00
V2S	sec_cm_config_regwen	edn_regwen	0.000s	0.000us	0	20	0.00
V2S	sec_cm_config_mubi	edn_alert	0.000s	0.000us	0	400	0.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	0.000s	0.000us	0	10	0.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	0.000s	0.000us	0	10	0.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	0.000s	0.000us	0	10	0.00
V2S	sec_cm_ctr_redun	edn_sec_cm	0.000s	0.000us	0	10	0.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.000s	0.000us	0	400	0.00
		edn_sec_cm	0.000s	0.000us	0	10	0.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.000s	0.000us	0	400	0.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	0.000s	0.000us	0	40	0.00
V2S		TOTAL			0	70	0.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	0.000s	0.000us	0	100	0.00
V3		TOTAL			0	100	0.00
		TOTAL			0	2260	0.00

Failure Buckets

• Job killed most likely because its dependent job failed. has 2264 failures:
  • Test edn_smoke has 100 failures.

    • 0.edn_smoke.5154694691310187588057348043293625795271448813201585105436391399411923278003
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_smoke/latest/run.log

    • 1.edn_smoke.90927789150950642459061461743976345811136861519320200027937333258821705619879
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_smoke/latest/run.log

    • ... and 98 more failures.

  • Test edn_regwen has 20 failures.

    • 0.edn_regwen.93043769701924560421599989001902474393400659643926834783097184613663694626076
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_regwen/latest/run.log

    • 1.edn_regwen.15930708888514160527353440954982347365167728207021141312464948610939440787058
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_regwen/latest/run.log

    • ... and 18 more failures.

  • Test edn_genbits has 600 failures.

    • 0.edn_genbits.52836279287473905080072493714698739423819940499213452017460372481466276053234
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_genbits/latest/run.log

    • 1.edn_genbits.34305394406432163128712192048966264079399058710382478134386732883125451099920
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_genbits/latest/run.log

    • ... and 598 more failures.

  • Test edn_stress_all has 100 failures.

    • 0.edn_stress_all.79249437332878252366338395274027310556826794101171922112291102904930164012423
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all/latest/run.log

    • 1.edn_stress_all.5495162225268331310324888953239312543801107970391594762124611716335257437977
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_stress_all/latest/run.log

    • ... and 98 more failures.

  • Test edn_stress_all_with_rand_reset has 100 failures.

    • 0.edn_stress_all_with_rand_reset.107187508347921808793105790546119702149548014061081214080795525444889378059667
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

    • 1.edn_stress_all_with_rand_reset.30462883371930976163076003761341938205405881287989778314462186413932458833386
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log

    • ... and 98 more failures.

  • ... and 17 more tests.
• Job returned non-zero exit code has 4 failures:

  • Test default has 2 failures.

    • default
      Log /nightly/current_run/scratch/master/edn-sim-vcs/default/build.log

          File "/nightly/current_run/opentitan/hw/formal/tools/csr_assert_gen/csr_assert_gen.py", line 62, in <module>
            main()
            ~~~~^^
          File "/nightly/current_run/opentitan/hw/formal/tools/csr_assert_gen/csr_assert_gen.py", line 30, in main
            gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
                             ~~~~^^^^^^^^^^^^^^^
        FileNotFoundError: [Errno 2] No such file or directory: '/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_sva-csr_assert_gen_0.1-3d387bb0e518b1118852a68f330120acb02137bd0daf464c8d791c909b9efe25/csr_assert_gen_input.yml'
        ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_sva-csr_assert_gen_0.1-3d387bb0e518b1118852a68f330120acb02137bd0daf464c8d791c909b9efe25"
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
      

    • default
      Log /nightly/current_run/scratch/master/edn-sim-vcs/default/build.log

          File "/nightly/current_run/opentitan/hw/formal/tools/csr_assert_gen/csr_assert_gen.py", line 62, in <module>
            main()
            ~~~~^^
          File "/nightly/current_run/opentitan/hw/formal/tools/csr_assert_gen/csr_assert_gen.py", line 30, in main
            gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
                             ~~~~^^^^^^^^^^^^^^^
        FileNotFoundError: [Errno 2] No such file or directory: '/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_sva-csr_assert_gen_0.1-3d387bb0e518b1118852a68f330120acb02137bd0daf464c8d791c909b9efe25/csr_assert_gen_input.yml'
        ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_sva-csr_assert_gen_0.1-3d387bb0e518b1118852a68f330120acb02137bd0daf464c8d791c909b9efe25"
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
      

  • Test cover_reg_top has 2 failures.

    • cover_reg_top
      Log /nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/build.log

            return gen_fpv.gen_fpv(obj, outdir)
                   ~~~~~~~~~~~~~~~^^^^^^^^^^^^^
          File "/nightly/current_run/opentitan/util/reggen/gen_fpv.py", line 46, in gen_fpv
            with open(reg_top_path, 'w', encoding='UTF-8') as fout:
                 ~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
        FileNotFoundError: [Errno 2] No such file or directory: './edn_csr_assert_fpv.sv'
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
        Error: CSR assert gen failed:
        Command '['/nightly/current_run/opentitan/util/regtool.py', '-f', '-t', '.', '/nightly/current_run/opentitan/hw/ip/edn/data/edn.hjson']' returned non-zero exit status 1.
        ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_sva-csr_assert_gen_0.1-3d387bb0e518b1118852a68f330120acb02137bd0daf464c8d791c909b9efe25"
      

    • cover_reg_top
      Log /nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/build.log

                   ~~~~~~~~~~~~~~~^^^^^^^^^^^^^
          File "/nightly/current_run/opentitan/util/reggen/gen_fpv.py", line 46, in gen_fpv
            with open(reg_top_path, 'w', encoding='UTF-8') as fout:
                 ~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
        FileNotFoundError: [Errno 2] No such file or directory: './edn_csr_assert_fpv.sv'
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
        Error: CSR assert gen failed:
        Command '['/nightly/current_run/opentitan/util/regtool.py', '-f', '-t', '.', '/nightly/current_run/opentitan/hw/ip/edn/data/edn.hjson']' returned non-zero exit status 1.
        ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_sva-csr_assert_gen_0.1-3d387bb0e518b1118852a68f330120acb02137bd0daf464c8d791c909b9efe25"
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1