HMAC Simulation Results

Sunday December 07 2025 00:12:41 UTC

GitHub Revision: 9ce72b8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.180s	1377.435us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.340s	126.841us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.250s	38.800us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.590s	1231.806us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.730s	1988.884us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	179.220s	92977.567us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.250s	38.800us	20	20	100.00
		hmac_csr_aliasing	8.730s	1988.884us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	100.000s	36036.179us	10	10	100.00
V2	back_pressure	hmac_back_pressure	87.560s	3343.460us	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	256.050s	13221.231us	30	30	100.00
		hmac_test_sha384_vectors	550.900s	13918.318us	75	75	100.00
		hmac_test_sha512_vectors	524.310s	58297.118us	75	75	100.00
		hmac_test_hmac256_vectors	15.320s	679.507us	50	50	100.00
		hmac_test_hmac384_vectors	18.530s	2351.433us	60	60	100.00
		hmac_test_hmac512_vectors	18.180s	349.841us	75	75	100.00
V2	burst_wr	hmac_burst_wr	35.350s	2551.177us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	833.170s	93975.088us	10	10	100.00
V2	error	hmac_error	132.690s	8011.305us	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	114.200s	13651.330us	10	10	100.00
V2	save_and_restore	hmac_smoke	16.180s	1377.435us	10	10	100.00
		hmac_long_msg	100.000s	36036.179us	10	10	100.00
		hmac_back_pressure	87.560s	3343.460us	25	25	100.00
		hmac_datapath_stress	833.170s	93975.088us	10	10	100.00
		hmac_burst_wr	35.350s	2551.177us	50	50	100.00
		hmac_stress_all	6506.500s	98209.326us	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.180s	1377.435us	10	10	100.00
		hmac_long_msg	100.000s	36036.179us	10	10	100.00
		hmac_back_pressure	87.560s	3343.460us	25	25	100.00
		hmac_datapath_stress	833.170s	93975.088us	10	10	100.00
		hmac_wipe_secret	114.200s	13651.330us	10	10	100.00
		hmac_test_sha256_vectors	256.050s	13221.231us	30	30	100.00
		hmac_test_sha384_vectors	550.900s	13918.318us	75	75	100.00
		hmac_test_sha512_vectors	524.310s	58297.118us	75	75	100.00
		hmac_test_hmac256_vectors	15.320s	679.507us	50	50	100.00
		hmac_test_hmac384_vectors	18.530s	2351.433us	60	60	100.00
		hmac_test_hmac512_vectors	18.180s	349.841us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.180s	1377.435us	10	10	100.00
		hmac_long_msg	100.000s	36036.179us	10	10	100.00
		hmac_back_pressure	87.560s	3343.460us	25	25	100.00
		hmac_datapath_stress	833.170s	93975.088us	10	10	100.00
		hmac_burst_wr	35.350s	2551.177us	50	50	100.00
		hmac_error	132.690s	8011.305us	10	10	100.00
		hmac_wipe_secret	114.200s	13651.330us	10	10	100.00
		hmac_test_sha256_vectors	256.050s	13221.231us	30	30	100.00
		hmac_test_sha384_vectors	550.900s	13918.318us	75	75	100.00
		hmac_test_sha512_vectors	524.310s	58297.118us	75	75	100.00
		hmac_test_hmac256_vectors	15.320s	679.507us	50	50	100.00
		hmac_test_hmac384_vectors	18.530s	2351.433us	60	60	100.00
		hmac_test_hmac512_vectors	18.180s	349.841us	75	75	100.00
		hmac_stress_all	6506.500s	98209.326us	50	50	100.00
V2	stress_all	hmac_stress_all	6506.500s	98209.326us	50	50	100.00
V2	alert_test	hmac_alert_test	0.930s	39.604us	50	50	100.00
V2	intr_test	hmac_intr_test	0.940s	26.904us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.940s	420.930us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.940s	420.930us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.340s	126.841us	5	5	100.00
		hmac_csr_rw	1.250s	38.800us	20	20	100.00
		hmac_csr_aliasing	8.730s	1988.884us	5	5	100.00
		hmac_same_csr_outstanding	2.990s	347.972us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.340s	126.841us	5	5	100.00
		hmac_csr_rw	1.250s	38.800us	20	20	100.00
		hmac_csr_aliasing	8.730s	1988.884us	5	5	100.00
		hmac_same_csr_outstanding	2.990s	347.972us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.540s	172.734us	5	5	100.00
		hmac_tl_intg_err	5.090s	1100.643us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.090s	1100.643us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.180s	1377.435us	10	10	100.00
V3	stress_reset	hmac_stress_reset	7.170s	275.039us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	973.980s	127674.752us	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.200s	344.630us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.17	99.95	96.85	100.00	100.00	99.83	97.61	99.95