KEYMGR Simulation Results

Sunday December 07 2025 00:12:41 UTC

GitHub Revision: `9ce72b8`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	28.750s	3163.781us	50	50	100.00
V1	random	keymgr_random	67.360s	12142.950us	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.770s	32.313us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.510s	112.532us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	18.910s	12269.684us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.070s	371.041us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.250s	46.012us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.510s	112.532us	20	20	100.00
		keymgr_csr_aliasing	9.070s	371.041us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	102.600s	5927.667us	50	50	100.00
V2	sideload	keymgr_sideload	33.090s	1569.281us	50	50	100.00
		keymgr_sideload_kmac	39.770s	6100.612us	50	50	100.00
		keymgr_sideload_aes	34.790s	2706.691us	50	50	100.00
		keymgr_sideload_otbn	40.600s	1779.736us	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	42.420s	1508.217us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	21.800s	1063.772us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	10.740s	2422.714us	48	50	96.00
V2	invalid_sw_input	keymgr_sw_invalid_input	35.250s	3551.355us	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	30.550s	7306.647us	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	13.360s	4339.384us	50	50	100.00
V2	stress_all	keymgr_stress_all	365.220s	69324.766us	50	50	100.00
V2	intr_test	keymgr_intr_test	1.210s	52.504us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.430s	37.718us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.470s	651.320us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.470s	651.320us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.770s	32.313us	5	5	100.00
		keymgr_csr_rw	1.510s	112.532us	20	20	100.00
		keymgr_csr_aliasing	9.070s	371.041us	5	5	100.00
		keymgr_same_csr_outstanding	3.710s	102.410us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.770s	32.313us	5	5	100.00
		keymgr_csr_rw	1.510s	112.532us	20	20	100.00
		keymgr_csr_aliasing	9.070s	371.041us	5	5	100.00
		keymgr_same_csr_outstanding	3.710s	102.410us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	tl_intg_err	keymgr_tl_intg_err	7.780s	1344.728us	20	20	100.00
		keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.690s	275.618us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.690s	275.618us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.690s	275.618us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.690s	275.618us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	22.710s	6770.038us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.780s	1344.728us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.690s	275.618us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	102.600s	5927.667us	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_csr_rw	1.510s	112.532us	20	20	100.00
		keymgr_random	67.360s	12142.950us	50	50	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_csr_rw	1.510s	112.532us	20	20	100.00
		keymgr_random	67.360s	12142.950us	50	50	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_csr_rw	1.510s	112.532us	20	20	100.00
		keymgr_random	67.360s	12142.950us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	21.800s	1063.772us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	30.550s	7306.647us	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	30.550s	7306.647us	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	67.360s	12142.950us	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	21.020s	978.383us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	16.770s	944.488us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	21.800s	1063.772us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	16.770s	944.488us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	16.770s	944.488us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	16.770s	944.488us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.090s	637.198us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	16.770s	944.488us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	17.610s	2127.971us	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1084	1110	97.66

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	99.13	98.22	98.40	100.00	99.01	97.72	91.18

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test keymgr_stress_all_with_rand_reset has 21 failures.
  - 1.keymgr_stress_all_with_rand_reset.4639032973878755279399143052835799773519800498739494199407510832085561563916
    Line 555, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 405056005 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 405056005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.keymgr_stress_all_with_rand_reset.93142196357291313167070238604235764738863120077087273341326431986495515769388
    Line 302, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 204806439 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 204806439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.

UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 2 failures:

Test keymgr_kmac_rsp_err has 2 failures.

11.keymgr_kmac_rsp_err.108360145546030333158810135160902189695472117718395542423024179696506360482733
Line 262, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  28084929 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  28084929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.keymgr_kmac_rsp_err.97862922526114912511934584488478816653800115506981106920996152016349258699825
Line 200, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  47310314 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  47310314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 35.keymgr_stress_all_with_rand_reset.33525773201130276590334268892631088243218368810690132699290093043054712821261
    Line 202, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 429538290 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 429538290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 44.keymgr_stress_all_with_rand_reset.75498900977769874030600863974883557714362085692249311285259770191161435365574
    Line 239, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  41645517 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_1
  UVM_INFO @  41645517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

46.keymgr_stress_all_with_rand_reset.17593162524455908338330689270720526642560516512221771126265741544905411571406
Line 367, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 190875982 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (21810387338661178124645797227949787383584568304075135060319941136714755696131974345534174686013144767277579851633738636091615812944277752576675047401061784787377344663061252890152501111569447622853564383845728957984740808429293693010129257126764282237141250142198760540187512358065243878732486832212917783998920388554371388767534142598861898981744 [0x5b46362785ba6c998a34f2340d3bced90000000000000000ae34ac61d20dfb4cb7dc201eda8286b48f26626e9ecf585e6ed80418b971d6d6a2826e846e7ac4135e8aa5c33235b5ea6b85d5cbae564af69ca14a764a69b9f3803e5e56ff951de4c8adf71a9e7104bae5cfc033ed7b61f869802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170] vs 2282246009031264311963098872646846248351986038448386612632321608586669637774604978368176067928042290552133483243796341206758322761535750674172594038065692505509719319032890946939448977792164406688206868120144459773334917968051512037035094067920704848410487663105929214777960573961470835255173270987053147901060727864732924196572657688944 [0x290566a926b98f50665a89ea31dea4e999e17e77d5e51a55e7fa2a73b7dc201eda8286b48f26626e9ecf585e6ed80418b971d6d6a2826e846e7ac4135e8aa5c33235b5ea6b85d5cbae564af69ca14a764a69b9f3803e5e56ff951de4c8adf71a9e7104bae5cfc033ed7b61f869802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170]) cdi_type: Attestation

   HardwareRevisionSecret act: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170, exp: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170
   RomDigest act: 0x9ca14a764a69b9f3803e5e56ff951de4c8adf71a9e7104bae5cfc033ed7b61f8, exp: 0x9ca14a764a69b9f3803e5e56ff951de4c8adf71a9e7104bae5cfc033ed7b61f8
   HealthMeasurement act: 0x5e8aa5c33235b5ea6b85d5cbae564af6, exp: 0x5e8aa5c33235b5ea6b85d5cbae564af6