9ce72b8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 85.790s | 36942.732us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.030s | 36.907us | 10 | 10 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.230s | 36.400us | 40 | 40 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 13.040s | 5197.335us | 10 | 10 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 6.160s | 1415.341us | 10 | 10 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.000s | 100.559us | 40 | 40 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.230s | 36.400us | 40 | 40 | 100.00 |
| kmac_csr_aliasing | 6.160s | 1415.341us | 10 | 10 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 1.070s | 13.757us | 10 | 10 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.660s | 52.499us | 10 | 10 | 100.00 |
| V1 | TOTAL | 230 | 230 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 3183.080s | 500284.462us | 100 | 100 | 100.00 |
| V2 | burst_write | kmac_burst_write | 1366.790s | 30193.827us | 100 | 100 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 2083.760s | 323128.850us | 10 | 10 | 100.00 |
| kmac_test_vectors_sha3_256 | 1919.510s | 75875.385us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 1523.570s | 70910.285us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 1186.150s | 31886.736us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_shake_128 | 2066.310s | 96672.147us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_shake_256 | 2182.860s | 357145.558us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_kmac | 3.440s | 86.928us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 3.950s | 488.810us | 10 | 10 | 100.00 | ||
| V2 | sideload | kmac_sideload | 538.310s | 57299.975us | 100 | 100 | 100.00 |
| V2 | app | kmac_app | 387.150s | 123780.709us | 100 | 100 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 324.130s | 20063.981us | 20 | 20 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 415.630s | 141388.411us | 100 | 100 | 100.00 |
| V2 | error | kmac_error | 509.350s | 20477.539us | 99 | 100 | 99.00 |
| V2 | key_error | kmac_key_error | 18.650s | 9659.645us | 100 | 100 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 139.690s | 10076.358us | 85 | 100 | 85.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 46.130s | 1816.500us | 40 | 40 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 39.690s | 3842.566us | 40 | 40 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 73.090s | 30371.540us | 20 | 20 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 55.350s | 939.884us | 100 | 100 | 100.00 |
| V2 | stress_all | kmac_stress_all | 3137.250s | 96216.316us | 100 | 100 | 100.00 |
| V2 | intr_test | kmac_intr_test | 0.980s | 22.272us | 100 | 100 | 100.00 |
| V2 | alert_test | kmac_alert_test | 1.260s | 49.098us | 100 | 100 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.440s | 230.206us | 40 | 40 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.440s | 230.206us | 40 | 40 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.030s | 36.907us | 10 | 10 | 100.00 |
| kmac_csr_rw | 1.230s | 36.400us | 40 | 40 | 100.00 | ||
| kmac_csr_aliasing | 6.160s | 1415.341us | 10 | 10 | 100.00 | ||
| kmac_same_csr_outstanding | 2.210s | 468.359us | 40 | 40 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.030s | 36.907us | 10 | 10 | 100.00 |
| kmac_csr_rw | 1.230s | 36.400us | 40 | 40 | 100.00 | ||
| kmac_csr_aliasing | 6.160s | 1415.341us | 10 | 10 | 100.00 | ||
| kmac_same_csr_outstanding | 2.210s | 468.359us | 40 | 40 | 100.00 | ||
| V2 | TOTAL | 1464 | 1480 | 98.92 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.950s | 187.703us | 40 | 40 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.950s | 187.703us | 40 | 40 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.950s | 187.703us | 40 | 40 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.950s | 187.703us | 40 | 40 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 4.620s | 1033.020us | 40 | 40 | 100.00 |
| V2S | tl_intg_err | kmac_tl_intg_err | 3.710s | 142.026us | 40 | 40 | 100.00 |
| kmac_sec_cm | 98.150s | 33359.407us | 10 | 10 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 3.710s | 142.026us | 40 | 40 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 55.350s | 939.884us | 100 | 100 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 85.790s | 36942.732us | 100 | 100 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 538.310s | 57299.975us | 100 | 100 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.950s | 187.703us | 40 | 40 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 98.150s | 33359.407us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 98.150s | 33359.407us | 10 | 10 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 98.150s | 33359.407us | 10 | 10 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 85.790s | 36942.732us | 100 | 100 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 55.350s | 939.884us | 100 | 100 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 98.150s | 33359.407us | 10 | 10 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 290.320s | 21832.868us | 20 | 20 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 85.790s | 36942.732us | 100 | 100 | 100.00 |
| V2S | TOTAL | 150 | 150 | 100.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 422.040s | 4951.075us | 17 | 20 | 85.00 |
| V3 | TOTAL | 17 | 20 | 85.00 | |||
| TOTAL | 1861 | 1880 | 98.99 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.15 | 99.27 | 94.45 | 99.89 | 79.58 | 97.15 | 97.83 | 97.86 |
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:
0.kmac_sideload_invalid.61928039840840953495190161270797705234847078085509202519602018437444852587501
Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10027148135 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x71b1e000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10027148135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.kmac_sideload_invalid.13367279271395119688726656974715861592810486291282516499056633855877150670407
Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/22.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10057260229 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x20b01000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10057260229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 3 failures:
2.kmac_stress_all_with_rand_reset.10412670158951622617128844981183034014684228283772586549806585941140059273209
Line 217, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1450433513 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 1450433513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.kmac_stress_all_with_rand_reset.69815561516993828371121422268090997227922128969398510428636225098977382126732
Line 242, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7812504306 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 7812504306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
13.kmac_sideload_invalid.52697953925341589886117727289075008748945563105868277907082497786567455026566
Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/13.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10028133197 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2e592000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10028133197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.kmac_sideload_invalid.101210997097958255801256925630501789319093004119936954419751136221848112585116
Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/36.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10206304300 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6b104000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10206304300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
20.kmac_sideload_invalid.86457371352028650704121220904814827371676234390305997914663110666321945029678
Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10046287314 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa0d51000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10046287314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.kmac_sideload_invalid.82790490827104283781956829463615052852158313218593632384004340502063304777448
Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10047433033 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2d8f000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10047433033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
2.kmac_sideload_invalid.102665900583816580715422725860781703434478786059410750211058542946341448667249
Line 90, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10076358199 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcfdb1000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10076358199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
8.kmac_sideload_invalid.75996023261336079684837236674457730500690942442246345946007747620331497165650
Line 82, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10130972810 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb0933000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10130972810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
9.kmac_sideload_invalid.57824371834803996941121514312260859753351273831080860534144089497784970079152
Line 101, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10404783199 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x777fd000, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
UVM_INFO @ 10404783199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
12.kmac_sideload_invalid.75847566188442880967598337980646114603914293249890099107313387417109176963284
Line 86, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/12.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10066249474 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4229e000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10066249474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
15.kmac_sideload_invalid.30161606289283527462362519363909928359111438324560133911077813807452644205848
Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/15.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10056790788 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdc555000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10056790788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
24.kmac_sideload_invalid.62894717252562060915112042305829971375814318439977390914370769984946038349130
Line 94, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/24.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10373533625 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x57805000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10373533625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
32.kmac_sideload_invalid.78948822791678793896211249636109549109555705668855906474160517743813338149636
Line 94, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10206082339 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4b8ac000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10206082339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
47.kmac_sideload_invalid.48585859873929664750446104068756901552670017987873362299502146569112761560607
Line 103, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/47.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10577404391 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1a465000, Comparison=CompareOpEq, exp_data=0x1, call_count=25)
UVM_INFO @ 10577404391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
48.kmac_error.10740537644542665208154625637094409077901996999587096878418714152493366664573
Line 203, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/48.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---