OTBN Simulation Results

Sunday December 07 2025 00:12:41 UTC

GitHub Revision: `9ce72b8`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	133.873us	1	1	100.00
V1	single_binary	otbn_single	166.000s	2416.499us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	30.808us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	24.029us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	140.455us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	21.593us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	56.807us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	24.029us	20	20	100.00
		otbn_csr_aliasing	5.000s	21.593us	5	5	100.00
V1	mem_walk	otbn_mem_walk	40.000s	4966.023us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	367.396us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	61.000s	286.897us	10	10	100.00
V2	multi_error	otbn_multi_err	58.000s	1258.202us	1	1	100.00
V2	back_to_back	otbn_multi	87.000s	252.151us	10	10	100.00
V2	stress_all	otbn_stress_all	91.000s	411.436us	10	10	100.00
V2	lc_escalation	otbn_escalate	23.000s	209.619us	58	60	96.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	34.791us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	24.000s	136.180us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	31.438us	50	50	100.00
V2	intr_test	otbn_intr_test	5.000s	20.918us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	100.795us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	100.795us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	30.808us	5	5	100.00
		otbn_csr_rw	6.000s	24.029us	20	20	100.00
		otbn_csr_aliasing	5.000s	21.593us	5	5	100.00
		otbn_same_csr_outstanding	4.000s	22.423us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	30.808us	5	5	100.00
		otbn_csr_rw	6.000s	24.029us	20	20	100.00
		otbn_csr_aliasing	5.000s	21.593us	5	5	100.00
		otbn_same_csr_outstanding	4.000s	22.423us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	10.000s	31.168us	10	10	100.00
		otbn_dmem_err	18.000s	58.110us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	17.000s	123.123us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	73.003us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	366.920us	5	5	100.00
		otbn_urnd_err	7.000s	30.168us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	6.000s	12.227us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	40.526us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	48.796us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	130.000s	2378.135us	2	5	40.00
		otbn_tl_intg_err	24.000s	295.798us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	56.000s	593.684us	17	20	85.00
V2S	prim_fsm_check	otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	133.873us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	18.000s	58.110us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	31.168us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	24.000s	295.798us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	23.000s	209.619us	58	60	96.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	31.168us	10	10	100.00
		otbn_dmem_err	18.000s	58.110us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	34.791us	5	5	100.00
		otbn_illegal_mem_acc	6.000s	12.227us	5	5	100.00
		otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	166.000s	2416.499us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	31.168us	10	10	100.00
		otbn_dmem_err	18.000s	58.110us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	34.791us	5	5	100.00
		otbn_illegal_mem_acc	6.000s	12.227us	5	5	100.00
		otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	23.000s	209.619us	58	60	96.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	31.168us	10	10	100.00
		otbn_dmem_err	18.000s	58.110us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	34.791us	5	5	100.00
		otbn_illegal_mem_acc	6.000s	12.227us	5	5	100.00
		otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	166.000s	2416.499us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	34.931us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	14.000s	48.927us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	92.000s	576.744us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	92.000s	576.744us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	28.000s	2013.371us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	211.144us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	41.751us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	41.751us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	41.442us	3	7	42.86
V2S	sec_cm_data_mem_sec_wipe	otbn_single	166.000s	2416.499us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	166.000s	2416.499us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	166.000s	2416.499us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	87.000s	252.151us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	166.000s	2416.499us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	166.000s	2416.499us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	13.000s	38.714us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	166.000s	2416.499us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	130.000s	2378.135us	2	5	40.00
V2S		TOTAL			152	163	93.25
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	420.000s	5698.407us	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			568	585	97.09

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.01	99.58	95.15	99.67	93.08	93.39	100.00	96.72	100.00

Failure Buckets

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 6 failures:

Test otbn_sec_wipe_err has 4 failures.

0.otbn_sec_wipe_err.10792467449048969333663886863708947642056967513062466279287781703589870694849
Line 124, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13424445 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  13424445 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  13424445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_sec_wipe_err.97255638035197428676727107511361802657862017256250095016398155808150046112177
Line 113, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 41442025 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  41442025 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  41442025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test otbn_escalate has 2 failures.

27.otbn_escalate.113775084072835307399256258273284337639735367369365768885371222186526643589477
Line 119, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/27.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15413202 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  15413202 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  15413202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

55.otbn_escalate.89932469922825830295594042512419061520678120580207340834896538700025610258579
Line 119, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/55.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15056431 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  15056431 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  15056431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

2.otbn_sec_cm.82685532026329955240618844630713727399839119894973462876205503200849036435812
Line 89, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 31438242 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 31438242 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 31438242 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 31438242 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 31438242 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

3.otbn_sec_cm.47422032578602493698639665624664233855832800360446722919929741763090877476709
Line 112, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 66601005 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 66601005 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 66601005 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 66601005 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 66601005 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 2.otbn_stress_all_with_rand_reset.70086350518426477059903287138929499974436212936913121691056976645924702727821
    Line 257, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 564733319 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 564733319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.otbn_stress_all_with_rand_reset.33670207323647436878336070738902864489505667107637791246009607665433748409073
    Line 556, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1503442433 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1503442433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.26106965402964691394726982920723076820592412951754960027985851511102790065103
    Line 551, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5698406692 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @ 5698406692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 15.otbn_passthru_mem_tl_intg_err.76792657887766038956741914764191560678028244454436243694586234360524464340077
    Line 83, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/15.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   3841281 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @   3841281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
- Test otbn_passthru_mem_tl_intg_err has 2 failures.
  - 1.otbn_passthru_mem_tl_intg_err.11620559200642721383118127490252694640635248736341518479681507947251204409755
    Line 93, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  19050625 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  19050625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.otbn_passthru_mem_tl_intg_err.107055016370007331743231104504426612193256863517198912312162251615562963366222
    Line 98, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  37996865 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  37996865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr otbn_reg_block.cmd (addr=*) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 1.otbn_rf_base_intg_err.102832942618026595005213101088089927985804856012112382970320784758647517332968
    Line 105, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 2013370745 ps: (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr otbn_reg_block.cmd (addr=0xe880010)
  UVM_INFO @ 2013370745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.92482804601661878680013331836005949647499137879215426494607477048736173749368
    Line 447, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5973505456 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 5973505456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```