9ce72b8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 6.000s | 25.001us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 21.000s | 13.072us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 21.000s | 11.786us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 23.000s | 379.352us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 21.000s | 32.469us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 21.000s | 80.945us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 21.000s | 11.786us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 21.000s | 32.469us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 3426.000s | 600000.000us | 26 | 50 | 52.00 |
| V2 | cnt_rollover | cnt_rollover | 87.000s | 5261.606us | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 13.000s | 19.327us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 10777.000s | 2134674.364us | 23 | 50 | 46.00 |
| V2 | alert_test | pattgen_alert_test | 3.000s | 30.530us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 21.000s | 14.271us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 22.000s | 126.644us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 22.000s | 126.644us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 21.000s | 13.072us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 21.000s | 11.786us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 21.000s | 32.469us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 21.000s | 28.868us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 21.000s | 13.072us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 21.000s | 11.786us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 21.000s | 32.469us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 21.000s | 28.868us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 340 | 85.00 | |||
| V2S | tl_intg_err | pattgen_sec_cm | 3.000s | 44.087us | 5 | 5 | 100.00 |
| pattgen_tl_intg_err | 21.000s | 104.536us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 21.000s | 104.536us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 149.000s | 22439.563us | 3 | 50 | 6.00 |
| V3 | TOTAL | 3 | 50 | 6.00 | |||
| Unmapped tests | pattgen_inactive_level | 273.000s | 10011.261us | 36 | 50 | 72.00 | |
| TOTAL | 458 | 570 | 80.35 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.53 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 96.95 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 46 failures:
1.pattgen_stress_all_with_rand_reset.39819163184697987767592704588210878172109810520842705465773932325706544729733
Line 115, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1785116643 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1785145043 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1785145043 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1785211709 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
3.pattgen_stress_all_with_rand_reset.78655162574940668751477021716057430444560278336679425857665967279535531465219
Line 113, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 667169167 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 667172244 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 667172244 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 667203495 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 44 more failures.
Job timed out after * minutes has 22 failures:
0.pattgen_perf.54249560903998293134021216143819286331326694430267512788366720760441141261305
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Job timed out after 60 minutes
1.pattgen_perf.85532907850129575232414004776568759421793923802687843939484259949598454894007
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 9 more failures.
7.pattgen_stress_all.42399385033821040623322666196666845034948323018735711350921463213721587332272
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
11.pattgen_stress_all.110498698994076389937119206363691280296549788910590510655488237468854029222653
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 9 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 16 failures:
0.pattgen_stress_all.74982500328092110195773937559594336234797114134355259298889462695192449069745
Line 142, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 56598001 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10237
4.pattgen_stress_all.33747630493215067926932235407952460128349386808641547861997685406414733060931
Line 132, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log
UVM_ERROR @ 2889230845705 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10110
... and 14 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 13 failures:
6.pattgen_perf.86406555387558429612087694948348965983874594678508334704026397783032996048287
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.pattgen_perf.26766753342432320612794431983410726327736133021590105996835190846635963872688
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 3 failures:
9.pattgen_inactive_level.79558179087446568564866509881767947615385046197310807489387246407616987044879
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10011261395 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa7eae8d0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10011261395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.pattgen_inactive_level.84644639443475336925043517625582979971158998711442324275304824347936402088596
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10025074187 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x129a6cd0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10025074187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 2 failures:
1.pattgen_inactive_level.22324482210985438615745164250909655112308215966821732500786849667337220503105
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10051358189 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x13cfe390, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10051358189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pattgen_inactive_level.1804039368376817983224832491617980505806315928943747511267425151414350361044
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10117533954 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x28617150, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10117533954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
2.pattgen_inactive_level.38658379654897217838431789090096744416634224337607964517486384436906041355687
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004665829 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x35871cd0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10004665829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pattgen_inactive_level.87755611647635047892691831179135501828440314177535073577040677457883828798133
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10005122768 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb3eabc90, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10005122768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
4.pattgen_inactive_level.115346799036120385040137094915017794626047782836749364668441392929337101993863
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10032928028 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfae37610, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10032928028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.pattgen_inactive_level.29469313831471308602564252501312550493639774469665698321053611610556196116678
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10127804918 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4f7a9190, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10127804918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 2 failures:
35.pattgen_inactive_level.43423671372940413022953485620446460881004822896116725402381783156213091830792
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10096824508 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xc511a650, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10096824508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.pattgen_inactive_level.13367093179085184089722834118797219046239443242378543698912709628254643068804
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10567744069 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x840c0410, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10567744069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 1 failures:
2.pattgen_stress_all_with_rand_reset.91180002239807635227187688314115795777783131602111067120170186029813180178398
Line 117, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 349940230 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
19.pattgen_inactive_level.96623265876019104869446278728856372414741887091106244687497801211847582334786
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10074252678 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x554f4690, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10074252678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
31.pattgen_inactive_level.37031128527532471848095659485418370708151448915915685627277177025751550922510
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10012119527 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf346f150, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10012119527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
34.pattgen_inactive_level.12824707570453129001897026916096878057047299076948526742976622298547306091781
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10021406200 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8ee68e90, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10021406200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---