ROM_CTRL/32KB Simulation Results

Sunday December 07 2025 00:12:41 UTC

GitHub Revision: 9ce72b8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	12.440s	300.574us	4	4	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.020s	710.255us	10	10	100.00
V1	csr_rw	rom_ctrl_csr_rw	11.820s	300.329us	40	40	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.340s	1028.276us	10	10	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	11.660s	297.359us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	12.950s	1788.651us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	11.820s	300.329us	40	40	100.00
		rom_ctrl_csr_aliasing	11.660s	297.359us	10	10	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.580s	698.436us	10	10	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.000s	288.036us	10	10	100.00
V1		TOTAL			134	134	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	12.050s	318.455us	4	4	100.00
V2	stress_all	rom_ctrl_stress_all	49.230s	1092.427us	40	40	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	19.900s	417.471us	4	4	100.00
V2	alert_test	rom_ctrl_alert_test	11.720s	287.691us	100	100	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.340s	289.076us	40	40	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.340s	289.076us	40	40	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.020s	710.255us	10	10	100.00
		rom_ctrl_csr_rw	11.820s	300.329us	40	40	100.00
		rom_ctrl_csr_aliasing	11.660s	297.359us	10	10	100.00
		rom_ctrl_same_csr_outstanding	15.910s	1271.686us	40	40	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.020s	710.255us	10	10	100.00
		rom_ctrl_csr_rw	11.820s	300.329us	40	40	100.00
		rom_ctrl_csr_aliasing	11.660s	297.359us	10	10	100.00
		rom_ctrl_same_csr_outstanding	15.910s	1271.686us	40	40	100.00
V2		TOTAL			228	228	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	235.740s	11161.571us	36	40	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	71.530s	6679.721us	40	40	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	536.760s	1078.159us	4	10	40.00
		rom_ctrl_tl_intg_err	150.630s	367.937us	40	40	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	536.760s	1078.159us	4	10	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	536.760s	1078.159us	4	10	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	235.740s	11161.571us	36	40	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	235.740s	11161.571us	36	40	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	235.740s	11161.571us	36	40	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	235.740s	11161.571us	36	40	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	235.740s	11161.571us	36	40	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	536.760s	1078.159us	4	10	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	536.760s	1078.159us	4	10	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	12.440s	300.574us	4	4	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	12.440s	300.574us	4	4	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	12.440s	300.574us	4	4	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	150.630s	367.937us	40	40	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	235.740s	11161.571us	36	40	90.00
		rom_ctrl_kmac_err_chk	19.900s	417.471us	4	4	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	235.740s	11161.571us	36	40	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	235.740s	11161.571us	36	40	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	235.740s	11161.571us	36	40	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	71.530s	6679.721us	40	40	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	536.760s	1078.159us	4	10	40.00
V2S		TOTAL			120	130	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	425.500s	10908.306us	40	40	100.00
V3		TOTAL			40	40	100.00
		TOTAL			522	532	98.12

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.46	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 4 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 4 failures.

    • 8.rom_ctrl_corrupt_sig_fatal_chk.67231625577110269404185354121282985789906541866552970641626543839905779991979
      Line 98, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 3029179321 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 3029179321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.rom_ctrl_corrupt_sig_fatal_chk.79389739352105270915956405216837428355409255335618776353651213719022092440469
      Line 102, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1090195208 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1090195208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 0.rom_ctrl_sec_cm.105396962385001233966171104942224901626479099654320751262025257005661475832548
      Line 131, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 18028825ps failed at 18028825ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 18048825ps failed at 18048825ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

    • 4.rom_ctrl_sec_cm.48564256515368786761521175637135234171244482461540469494519930546805999616970
      Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 2887434ps failed at 2887434ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 9909132ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 9909132ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 2.rom_ctrl_sec_cm.56817381774553357465529080191895146422556499176277566809148074807424130692362
      Line 223, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 14266594ps failed at 14266594ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 14266594ps failed at 14266594ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

    • 2.rom_ctrl_sec_cm.113606975385532974086365816775518009985829745355308875248564632136227974512645
      Line 219, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 14103971ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 14103971ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 14103971ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 0.rom_ctrl_sec_cm.72853227162389065170881469925726020591497332589793536708130110149639995608158
      Line 241, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 28839780ps failed at 28839780ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 28839780ps failed at 28839780ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 3.rom_ctrl_sec_cm.86552373535690827781218502611305854569803594005903439769270042911447171987257
      Line 418, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 20952653ps failed at 20952653ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 20952653ps failed at 20952653ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'