RV_TIMER Simulation Results

Sunday December 07 2025 00:12:41 UTC

GitHub Revision: `9ce72b8`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.410s	645.237us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.680s	61.053us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.670s	22.668us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.630s	411.698us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.820s	62.262us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.090s	29.411us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.670s	22.668us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	62.262us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	2.410s	786.898us	1	20	5.00
V2	disabled	rv_timer_disabled	2.890s	2048.527us	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	389.220s	1152163.428us	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	389.220s	1152163.428us	10	10	100.00
V2	stress	rv_timer_stress_all	8.100s	6589.305us	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.770s	89.189us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.700s	11.934us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.140s	582.228us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.140s	582.228us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.680s	61.053us	5	5	100.00
		rv_timer_csr_rw	0.670s	22.668us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	62.262us	5	5	100.00
		rv_timer_same_csr_outstanding	0.820s	57.493us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.680s	61.053us	5	5	100.00
		rv_timer_csr_rw	0.670s	22.668us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	62.262us	5	5	100.00
		rv_timer_same_csr_outstanding	0.820s	57.493us	20	20	100.00
V2		TOTAL			191	210	90.95
V2S	tl_intg_err	rv_timer_tl_intg_err	1.780s	6539.642us	20	20	100.00
		rv_timer_sec_cm	0.960s	92.744us	5	5	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.780s	6539.642us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	3.170s	370.543us	1	10	10.00
V3	max_value	rv_timer_max	0.870s	157.467us	1	10	10.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	70.680s	7485.551us	16	20	80.00
V3		TOTAL			18	40	45.00
		TOTAL			309	350	88.29

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.47	100.00	100.00	100.00	--	100.00	96.82	100.00

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 28 failures:
- Test rv_timer_min has 9 failures.
  - 0.rv_timer_min.96790800340373109924921659616356474863690133736536785238507746407536197119984
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 370543061 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x640af304) == 0x1
  UVM_INFO @ 370543061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_min.30432223317137574722247140860415597179800198826784141099242320713932873572160
    Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
```
  UVM_FATAL @  78110625 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x701a8704) == 0x1
  UVM_INFO @  78110625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
- Test rv_timer_random_reset has 19 failures.
  - 0.rv_timer_random_reset.15951837980238027471506039036339515560398405537441045331455522760766519568806
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 976250691 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe43cd704) == 0x1
  UVM_INFO @ 976250691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.54106758757596782915416845760554443494773780137331395087770223497359019553615
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 874667064 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe8686f04) == 0x1
  UVM_INFO @ 874667064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
- Test rv_timer_max has 9 failures.
  - 0.rv_timer_max.51965654204030724296492188551369494105390831555165291989394648420203290801557
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @  83758554 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  83758554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.75430697339838518209318745987319207945391327876825568474012551941069115385331
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 106520655 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 106520655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 3 failures:

Test rv_timer_stress_all_with_rand_reset has 3 failures.

1.rv_timer_stress_all_with_rand_reset.40290199672592323501460245699369784314674963811916568495808054454480729127335
Line 194, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2746544194 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2746544194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.rv_timer_stress_all_with_rand_reset.54287856483219576015524009741232684604307724724531125681181417222362971435926
Line 138, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/13.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6701494029 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6701494029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 9.rv_timer_stress_all_with_rand_reset.57626068558850404757571790026946215811182268628521121102713462411520448484238
    Line 160, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/9.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10314914195 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 10314914195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```