SRAM_CTRL/MAIN Simulation Results

Sunday December 07 2025 00:12:41 UTC

GitHub Revision: `9ce72b8`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	121.900s	7974.913us	100	100	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.080s	20.268us	10	10	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.070s	61.486us	40	40	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.920s	616.849us	10	10	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.120s	36.415us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.040s	1469.491us	37	40	92.50
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.070s	61.486us	40	40	100.00
		sram_ctrl_csr_aliasing	1.120s	36.415us	10	10	100.00
V1	mem_walk	sram_ctrl_mem_walk	356.880s	20690.759us	100	100	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	179.670s	22267.913us	100	100	100.00
V1		TOTAL			407	410	99.27
V2	multiple_keys	sram_ctrl_multiple_keys	1659.720s	46307.597us	100	100	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	413.400s	35965.566us	100	100	100.00
V2	bijection	sram_ctrl_bijection	2842.240s	638595.649us	100	100	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1287.410s	91151.046us	100	100	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	111.280s	116462.747us	100	100	100.00
V2	executable	sram_ctrl_executable	1749.420s	19050.017us	100	100	100.00
V2	partial_access	sram_ctrl_partial_access	105.230s	987.237us	100	100	100.00
		sram_ctrl_partial_access_b2b	572.450s	73710.934us	100	100	100.00
V2	max_throughput	sram_ctrl_max_throughput	116.130s	1525.602us	100	100	100.00
		sram_ctrl_throughput_w_partial_write	112.760s	804.090us	100	100	100.00
		sram_ctrl_throughput_w_readback	109.550s	291.024us	100	100	100.00
V2	regwen	sram_ctrl_regwen	1401.280s	27953.195us	100	100	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.620s	6701.086us	100	100	100.00
V2	stress_all	sram_ctrl_stress_all	6710.880s	903849.222us	100	100	100.00
V2	alert_test	sram_ctrl_alert_test	1.060s	14.539us	100	100	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.820s	541.201us	40	40	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.820s	541.201us	40	40	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.080s	20.268us	10	10	100.00
		sram_ctrl_csr_rw	1.070s	61.486us	40	40	100.00
		sram_ctrl_csr_aliasing	1.120s	36.415us	10	10	100.00
		sram_ctrl_same_csr_outstanding	1.210s	31.011us	40	40	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.080s	20.268us	10	10	100.00
		sram_ctrl_csr_rw	1.070s	61.486us	40	40	100.00
		sram_ctrl_csr_aliasing	1.120s	36.415us	10	10	100.00
		sram_ctrl_same_csr_outstanding	1.210s	31.011us	40	40	100.00
V2		TOTAL			1580	1580	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	79.960s	100606.803us	40	40	100.00
V2S	tl_intg_err	sram_ctrl_tl_intg_err	3.200s	1295.987us	40	40	100.00
		sram_ctrl_sec_cm	1.030s	9.791us	0	10	0.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.030s	9.791us	0	10	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.200s	1295.987us	40	40	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1401.280s	27953.195us	100	100	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1401.280s	27953.195us	100	100	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.070s	61.486us	40	40	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1749.420s	19050.017us	100	100	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1749.420s	19050.017us	100	100	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1749.420s	19050.017us	100	100	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	111.280s	116462.747us	100	100	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	11.440s	9501.483us	89	100	89.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	79.960s	100606.803us	40	40	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	13.700s	13151.758us	74	100	74.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	121.900s	7974.913us	100	100	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	121.900s	7974.913us	100	100	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1749.420s	19050.017us	100	100	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.030s	9.791us	0	10	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	111.280s	116462.747us	100	100	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.030s	9.791us	0	10	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.030s	9.791us	0	10	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	121.900s	7974.913us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.030s	9.791us	0	10	0.00
V2S		TOTAL			243	290	83.79
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	586.210s	2281.471us	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			2330	2380	97.90

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.41	99.11	92.90	90.71	100.00	98.02	95.83	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 25 failures:
- Test sram_ctrl_readback_err has 25 failures.
  - 0.sram_ctrl_readback_err.30594681044304944783499269039146182577908266957246294841122423313840545809125
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  26411010 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x75) != exp (0x44)
  UVM_INFO @  26411010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.sram_ctrl_readback_err.94375312781654543249714513067033644883233628679519766653926776389246890547269
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  77106417 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x25) != exp (0x67)
  UVM_INFO @  77106417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 23 more failures.
Offending 'reqfifo_rvalid' has 11 failures:
- Test sram_ctrl_mubi_enc_err has 11 failures.
  - 4.sram_ctrl_mubi_enc_err.78616909603928646086598602659462560331703475315925319097107936273725019114432
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  59436807 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  59436807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.sram_ctrl_mubi_enc_err.89964870921771202779984789694123865053782438110129686005058492023683884215521
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 116859928 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 116859928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 9 failures:
- Test sram_ctrl_sec_cm has 9 failures.
  - 0.sram_ctrl_sec_cm.84082824770397910616702491596646344705882015322883142581052887901968431359644
    Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   4279535 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   4279535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.sram_ctrl_sec_cm.56901052665883427130208858844336069604906533497089175342761428554072389436894
    Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   9790775 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   9790775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.115137221697255526357133531698095690118962629637883120061559942807298599173728
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  72362661 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (11 [0xb] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  72362661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 2.sram_ctrl_csr_mem_rw_with_rand_reset.92308429465623272619057483796220576183624299389668108245836230772027097666466
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  44968377 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @  44968377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 18.sram_ctrl_csr_mem_rw_with_rand_reset.107980290075045337256755584291945004074214666330875901553566996426689268603531
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  59792419 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: 0x0
  UVM_INFO @  59792419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 3.sram_ctrl_sec_cm.585301818708179036429755648257453436349684918250927427576611970153199122470
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   1906490 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1906490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3674) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_readback_err has 1 failures.

26.sram_ctrl_readback_err.88864175821695116266786508671472929421190325407403341809516658771074151740576
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/26.sram_ctrl_readback_err/latest/run.log

  UVM_ERROR @ 2738889621 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3674) { a_addr: 'h1e871530  a_data: 'h19  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hfd  a_opcode: 'h0  a_user: 'h2639d  d_param: 'h0  d_source: 'hfd  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2738889621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---