Simulation Results: adc_ctrl

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.37 %
  • code
  • 98.74 %
  • assert
  • 95.95 %
  • func
  • 91.43 %
  • line
  • 99.05 %
  • branch
  • 98.64 %
  • cond
  • 96.03 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
96.79%
V2S
100.00%
V3
86.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
adc_ctrl_smoke 21.210s 6030.170us 50 50 100.00
csr_hw_reset 5 5 100.00
adc_ctrl_csr_hw_reset 4.470s 1170.869us 5 5 100.00
csr_rw 20 20 100.00
adc_ctrl_csr_rw 2.540s 510.282us 20 20 100.00
csr_bit_bash 5 5 100.00
adc_ctrl_csr_bit_bash 118.150s 52279.432us 5 5 100.00
csr_aliasing 5 5 100.00
adc_ctrl_csr_aliasing 7.200s 1172.326us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 3.020s 518.282us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
adc_ctrl_csr_rw 2.540s 510.282us 20 20 100.00
adc_ctrl_csr_aliasing 7.200s 1172.326us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 50 50 100.00
adc_ctrl_filters_polled 1245.610s 491857.405us 50 50 100.00
filters_polled_fixed 50 50 100.00
adc_ctrl_filters_polled_fixed 1210.570s 486387.240us 50 50 100.00
filters_interrupt 48 50 96.00
adc_ctrl_filters_interrupt 1131.550s 498118.826us 48 50 96.00
filters_interrupt_fixed 50 50 100.00
adc_ctrl_filters_interrupt_fixed 1130.920s 496324.356us 50 50 100.00
filters_wakeup 50 50 100.00
adc_ctrl_filters_wakeup 1642.670s 644661.945us 50 50 100.00
filters_wakeup_fixed 50 50 100.00
adc_ctrl_filters_wakeup_fixed 1358.460s 610196.594us 50 50 100.00
filters_both 44 50 88.00
adc_ctrl_filters_both 1099.170s 493564.610us 44 50 88.00
clock_gating 33 50 66.00
adc_ctrl_clock_gating 1256.690s 548408.255us 33 50 66.00
poweron_counter 50 50 100.00
adc_ctrl_poweron_counter 17.950s 5162.478us 50 50 100.00
lowpower_counter 50 50 100.00
adc_ctrl_lowpower_counter 132.630s 43779.055us 50 50 100.00
fsm_reset 50 50 100.00
adc_ctrl_fsm_reset 379.420s 127625.057us 50 50 100.00
stress_all 48 50 96.00
adc_ctrl_stress_all 2721.200s 10000000.000us 48 50 96.00
alert_test 50 50 100.00
adc_ctrl_alert_test 2.530s 533.143us 50 50 100.00
intr_test 50 50 100.00
adc_ctrl_intr_test 2.690s 508.367us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
adc_ctrl_tl_errors 3.910s 453.020us 20 20 100.00
tl_d_illegal_access 20 20 100.00
adc_ctrl_tl_errors 3.910s 453.020us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
adc_ctrl_csr_hw_reset 4.470s 1170.869us 5 5 100.00
adc_ctrl_csr_rw 2.540s 510.282us 20 20 100.00
adc_ctrl_csr_aliasing 7.200s 1172.326us 5 5 100.00
adc_ctrl_same_csr_outstanding 20.360s 5075.542us 20 20 100.00
tl_d_partial_access 50 50 100.00
adc_ctrl_csr_hw_reset 4.470s 1170.869us 5 5 100.00
adc_ctrl_csr_rw 2.540s 510.282us 20 20 100.00
adc_ctrl_csr_aliasing 7.200s 1172.326us 5 5 100.00
adc_ctrl_same_csr_outstanding 20.360s 5075.542us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
adc_ctrl_sec_cm 13.770s 4046.138us 5 5 100.00
adc_ctrl_tl_intg_err 19.930s 8076.942us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
adc_ctrl_tl_intg_err 19.930s 8076.942us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 43 50 86.00
adc_ctrl_stress_all_with_rand_reset 2538.010s 10000000.000us 43 50 86.00

Error Messages

   Test seed line log context
Offending '(np_sample_cnt_q == '0)'
adc_ctrl_stress_all_with_rand_reset 99178279019773750398151787681200883276594631115557862459858003700890338771997 424
Offending '(np_sample_cnt_q == '0)'
UVM_ERROR @ 11230808647 ps: (adc_ctrl_fsm.sv:386) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 11230808647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state
adc_ctrl_filters_both 23502765260679885906033775956312428746760030808329599223329522957174417842819 334
UVM_ERROR @ 333905001732 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 333905001732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 105663592123850368025083023625193373435718940371574229172148966973205518622143 350
UVM_ERROR @ 486757119552 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 486757119552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 17733775916055624137804383540321401565535783383445599149406530033851975463747 334
UVM_ERROR @ 244379598144 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 244379598144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 45184472387107421494948484365968538152357120149706578663759417121290219591814 318
UVM_ERROR @ 81993455439 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 81993455439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 99254532917377982799727688537795942983069663915969703605769676665660502159568 335
UVM_ERROR @ 291311514327 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 291311514327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 67904165607351029095630770631260963333695443487528512200944656010528055118132 318
UVM_ERROR @ 87729754778 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 87729754778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 16277675608444600908101495132135676829411215740108141523210842592648321313724 318
UVM_ERROR @ 88754581631 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 88754581631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 96099645737050650648610738801506055011310280988278885057215434208079976196527 318
UVM_ERROR @ 81391588723 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 81391588723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_clock_gating 74765056228736219783393629124796797659300653660711571916146895772685512195956 318
UVM_ERROR @ 25018086746 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 25018086746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 85329293351921109665211711140095761050306822973907750488649616148618919662082 318
UVM_ERROR @ 1735192596 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 1735192596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 5259357225725663891097718732021812841242071941544770650733436759788979127388 324
UVM_ERROR @ 2723770040 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 2723770040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 96120908451001812206736424332595939150256931747237863003466121432067091695710 318
UVM_ERROR @ 3140868045 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 3140868045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 7413382234105010442525772396799041626759734209798996270418827110031127466058 331
UVM_ERROR @ 6504429790 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 6504429790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 63445675436547337996141361378738781925032156716009396004015657855753075078254 335
UVM_ERROR @ 166324729478 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 166324729478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 76772093770945795656721832898460274487354111525603869732960589663836419755227 318
UVM_ERROR @ 5330319412 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 5330319412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 83817472691225743946220018913636857326344806140186655951771758224275740166511 335
UVM_ERROR @ 163147582142 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 163147582142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_clock_gating 6152792959828830067617110026272605907050958391201313086063720786524008292957 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 85831610120762221812130263714767222340544581084730643379721036656290700291842 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 51945925817880892937768086518563000571740724086917325889468358837762030007631 352
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 48382749128596714213143303749322465797941540425425620868105217624712866510848 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 104489979092415979995803187441924474254945871927868627581601680073999263700369 331
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 98588476759756593952792314667833525446924295235166815366855243928113374447221 365
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 110521107567545050260811663880419962721581784009179932614419194603650474027210 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 68472282338352651434191719808530157276969474397806793170913930123074831199891 352
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 47687647720598236946816375137698925262819765537740547909479034217478076190714 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 101407088212050001687556428869440447146799772449606796531334278128701066306873 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 84092299779643496469817621948265558338931930440965591270066299733824492155199 372
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 58860272712465799330316972367922259623277932433176613700099474234531375628751 350
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 93335845752495630453513557437645550590086162139725841594836678286212701055490 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 33881357325674293188579050079300266832663336186624799177432789648839222176958 338
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 56825948848508656735639028928868793540357638873070546468955362471335464271122 381
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 93945741225045107617778183644900599435039522972921918870765323017263346120006 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 106185247156397319245621535461395382587176463211459058278780687623149888366653 331
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---