Simulation Results: chip

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.29 %
  • code
  • 86.33 %
  • assert
  • 97.25 %
  • func
  • 99.28 %
  • line
  • 94.66 %
  • branch
  • 94.63 %
  • cond
  • 93.48 %
  • toggle
  • 91.73 %
  • FSM
  • 57.14 %
Validation stages
V1
95.70%
V2
93.01%
V2S
66.67%
V3
85.45%
unmapped
77.27%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 12 12 100.00
chip_sw_example_flash 214.830s 2543.863us 3 3 100.00
chip_sw_example_rom 124.760s 2625.711us 3 3 100.00
chip_sw_example_manufacturer 202.250s 2656.036us 3 3 100.00
chip_sw_example_concurrency 220.570s 2852.375us 3 3 100.00
csr_hw_reset 5 5 100.00
chip_csr_hw_reset 357.350s 7161.587us 5 5 100.00
csr_rw 20 20 100.00
chip_csr_rw 561.780s 6528.225us 20 20 100.00
csr_bit_bash 5 5 100.00
chip_csr_bit_bash 3806.290s 43417.629us 5 5 100.00
csr_aliasing 5 5 100.00
chip_csr_aliasing 6093.580s 33460.929us 5 5 100.00
csr_mem_rw_with_rand_reset 9 20 45.00
chip_csr_mem_rw_with_rand_reset 713.760s 10214.754us 9 20 45.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
chip_csr_aliasing 6093.580s 33460.929us 5 5 100.00
chip_csr_rw 561.780s 6528.225us 20 20 100.00
xbar_smoke 100 100 100.00
xbar_smoke 10.630s 253.750us 100 100 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 397.090s 4341.449us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 397.090s 4341.449us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 397.090s 4341.449us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 494.390s 4426.943us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 494.390s 4426.943us 5 5 100.00
chip_sw_uart_tx_rx_idx1 517.770s 3966.211us 5 5 100.00
chip_sw_uart_tx_rx_idx2 526.140s 4387.355us 5 5 100.00
chip_sw_uart_tx_rx_idx3 522.420s 4192.557us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 2241.490s 12841.647us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2324.170s 12782.557us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1398.240s 13315.359us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 10 10 100.00
chip_padctrl_attributes 239.710s 5551.760us 10 10 100.00
chip_padctrl_attributes 10 10 100.00
chip_padctrl_attributes 239.710s 5551.760us 10 10 100.00
chip_sw_sleep_pin_mio_dio_val 2 3 66.67
chip_sw_sleep_pin_mio_dio_val 192.020s 2942.821us 2 3 66.67
chip_sw_sleep_pin_wake 2 3 66.67
chip_sw_sleep_pin_wake 178.430s 3659.133us 2 3 66.67
chip_sw_sleep_pin_retention 3 3 100.00
chip_sw_sleep_pin_retention 227.030s 4194.505us 3 3 100.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1080.370s 14638.136us 5 5 100.00
chip_tap_straps_testunlock0 865.590s 10931.902us 5 5 100.00
chip_tap_straps_rma 588.060s 8148.939us 5 5 100.00
chip_tap_straps_prod 1439.180s 17880.630us 5 5 100.00
chip_sw_pattgen_ios 3 3 100.00
chip_sw_pattgen_ios 221.880s 3032.438us 3 3 100.00
chip_sw_sleep_pwm_pulses 3 3 100.00
chip_sw_sleep_pwm_pulses 998.680s 8549.343us 3 3 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 622.920s 6889.796us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 622.920s 6889.796us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 739.450s 7629.526us 3 3 100.00
chip_sw_ast_clk_rst_inputs 0 3 0.00
chip_sw_ast_clk_rst_inputs 3167.930s 21175.335us 0 3 0.00
chip_sw_ast_sys_clk_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 498.410s 4548.050us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 789.800s 6075.928us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4332.880s 18771.643us 3 3 100.00
chip_sw_aes_enc_jitter_en 232.890s 3134.999us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 832.470s 5849.990us 3 3 100.00
chip_sw_hmac_enc_jitter_en 267.310s 3150.576us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1144.420s 9377.843us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 257.880s 3528.143us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 514.340s 5543.662us 3 3 100.00
chip_sw_clkmgr_jitter 199.600s 3090.523us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 220.240s 3572.649us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 6 8 75.00
chip_sw_sensor_ctrl_alert 816.740s 8239.090us 3 5 60.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 347.380s 5410.552us 3 3 100.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 251.650s 2961.403us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 347.380s 5410.552us 3 3 100.00
chip_sw_smoketest 51 51 100.00
chip_sw_flash_scrambling_smoketest 181.700s 3279.596us 3 3 100.00
chip_sw_aes_smoketest 218.980s 3012.628us 3 3 100.00
chip_sw_aon_timer_smoketest 271.150s 3344.407us 3 3 100.00
chip_sw_clkmgr_smoketest 202.920s 2772.972us 3 3 100.00
chip_sw_csrng_smoketest 206.480s 3158.013us 3 3 100.00
chip_sw_entropy_src_smoketest 1119.100s 6907.881us 3 3 100.00
chip_sw_gpio_smoketest 258.950s 3371.746us 3 3 100.00
chip_sw_hmac_smoketest 249.760s 3451.437us 3 3 100.00
chip_sw_kmac_smoketest 208.060s 2470.107us 3 3 100.00
chip_sw_otbn_smoketest 1602.300s 9826.859us 3 3 100.00
chip_sw_pwrmgr_smoketest 325.500s 5537.565us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 377.310s 6851.414us 3 3 100.00
chip_sw_rv_plic_smoketest 260.500s 2940.382us 3 3 100.00
chip_sw_rv_timer_smoketest 193.880s 3209.577us 3 3 100.00
chip_sw_rstmgr_smoketest 167.310s 3231.397us 3 3 100.00
chip_sw_sram_ctrl_smoketest 191.970s 3054.472us 3 3 100.00
chip_sw_uart_smoketest 243.100s 3483.337us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 191.670s 3365.725us 3 3 100.00
chip_sw_rom_functests 3 3 100.00
rom_keymgr_functest 501.030s 4331.327us 3 3 100.00
chip_sw_boot 3 3 100.00
chip_sw_uart_tx_rx_bootstrap 12476.920s 62999.481us 3 3 100.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 3545.850s 14124.864us 3 3 100.00
chip_sw_rom_raw_unlock 3 3 100.00
rom_raw_unlock 257.890s 5435.929us 3 3 100.00
chip_sw_power_idle_load 0 3 0.00
chip_sw_power_idle_load 231.450s 3432.658us 0 3 0.00
chip_sw_power_sleep_load 0 3 0.00
chip_sw_power_sleep_load 262.550s 3347.781us 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 3 3 100.00
chip_sw_exit_test_unlocked_bootstrap 10856.440s 53809.241us 3 3 100.00
chip_sw_inject_scramble_seed 3 3 100.00
chip_sw_inject_scramble_seed 11417.110s 56844.437us 3 3 100.00
tl_d_oob_addr_access 3 30 10.00
chip_tl_errors 291.190s 3731.549us 3 30 10.00
tl_d_illegal_access 3 30 10.00
chip_tl_errors 291.190s 3731.549us 3 30 10.00
tl_d_outstanding_access 50 50 100.00
chip_csr_aliasing 6093.580s 33460.929us 5 5 100.00
chip_same_csr_outstanding 3720.410s 29338.227us 20 20 100.00
chip_csr_hw_reset 357.350s 7161.587us 5 5 100.00
chip_csr_rw 561.780s 6528.225us 20 20 100.00
tl_d_partial_access 50 50 100.00
chip_csr_aliasing 6093.580s 33460.929us 5 5 100.00
chip_same_csr_outstanding 3720.410s 29338.227us 20 20 100.00
chip_csr_hw_reset 357.350s 7161.587us 5 5 100.00
chip_csr_rw 561.780s 6528.225us 20 20 100.00
xbar_base_random_sequence 100 100 100.00
xbar_random 76.080s 2283.349us 100 100 100.00
xbar_random_delay 600 600 100.00
xbar_smoke_zero_delays 7.580s 60.641us 100 100 100.00
xbar_smoke_large_delays 111.590s 9924.121us 100 100 100.00
xbar_smoke_slow_rsp 94.970s 6444.698us 100 100 100.00
xbar_random_zero_delays 44.590s 663.410us 100 100 100.00
xbar_random_large_delays 498.620s 59977.682us 100 100 100.00
xbar_random_slow_rsp 452.920s 33338.572us 100 100 100.00
xbar_unmapped_address 200 200 100.00
xbar_unmapped_addr 53.820s 1472.314us 100 100 100.00
xbar_error_and_unmapped_addr 42.240s 1277.861us 100 100 100.00
xbar_error_cases 200 200 100.00
xbar_error_random 79.650s 2541.694us 100 100 100.00
xbar_error_and_unmapped_addr 42.240s 1277.861us 100 100 100.00
xbar_all_access_same_device 200 200 100.00
xbar_access_same_device 118.230s 3490.405us 100 100 100.00
xbar_access_same_device_slow_rsp 1041.950s 99082.606us 100 100 100.00
xbar_all_hosts_use_same_source_id 100 100 100.00
xbar_same_source 70.170s 2577.812us 100 100 100.00
xbar_stress_all 200 200 100.00
xbar_stress_all 507.680s 20996.566us 100 100 100.00
xbar_stress_all_with_error 534.580s 21393.478us 100 100 100.00
xbar_stress_with_reset 200 200 100.00
xbar_stress_all_with_rand_reset 711.080s 8538.489us 100 100 100.00
xbar_stress_all_with_reset_error 555.550s 20340.081us 100 100 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 3545.850s 14124.864us 3 3 100.00
rom_e2e_shutdown_output 3 3 100.00
rom_e2e_shutdown_output 3669.700s 35518.795us 3 3 100.00
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 3495.650s 15404.937us 3 3 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2715.090s 11914.858us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3838.160s 17335.276us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3735.710s 15873.989us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3535.700s 16063.952us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3363.530s 14868.781us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 27.090s 10.180us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 18.820s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 18.950s 10.340us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 24.390s 10.100us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 24.410s 10.300us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 20.810s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 18.030s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 26.740s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 20.700s 10.200us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 20.540s 10.160us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 19.070s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 17.090s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 17.640s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 17.170s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 25.390s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 17.770s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 19.660s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 23.890s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 30.580s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 19.180s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.380s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20.910s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 28.510s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 29.340s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 20.800s 10.260us 0 1 0.00
rom_e2e_asm_init 15 15 100.00
rom_e2e_asm_init_test_unlocked0 2796.380s 11961.947us 3 3 100.00
rom_e2e_asm_init_dev 3736.930s 15687.384us 3 3 100.00
rom_e2e_asm_init_prod 3949.510s 19038.554us 3 3 100.00
rom_e2e_asm_init_prod_end 3849.860s 16686.325us 3 3 100.00
rom_e2e_asm_init_rma 3746.830s 16518.268us 3 3 100.00
rom_e2e_keymgr_init 8 9 88.89
rom_e2e_keymgr_init_rom_ext_meas 7077.670s 29145.381us 2 3 66.67
rom_e2e_keymgr_init_rom_ext_no_meas 7197.440s 30072.365us 3 3 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 7300.250s 30191.414us 3 3 100.00
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 3694.310s 16093.096us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3445.510s 34964.350us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3445.510s 34964.350us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 208.980s 3320.075us 3 3 100.00
chip_sw_aes_enc_jitter_en 232.890s 3134.999us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 208.630s 2622.863us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 207.630s 2904.868us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_sideload_aes 2017.330s 12159.202us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 223.080s 2742.687us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 530.680s 5533.820us 3 3 100.00
chip_sw_all_escalation_resets 96 100 96.00
chip_sw_all_escalation_resets 598.040s 5935.229us 96 100 96.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 720.110s 5267.768us 3 3 100.00
chip_plic_all_irqs_10 338.530s 3311.106us 3 3 100.00
chip_plic_all_irqs_20 446.010s 4065.461us 3 3 100.00
chip_sw_alert_handler_entropy 3 3 100.00
chip_sw_alert_handler_entropy 251.520s 3394.173us 3 3 100.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 1353.460s 11852.242us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 354.770s 4964.941us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 232.280s 3423.436us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1151.370s 7902.994us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1289.960s 8000.619us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1029.810s 8212.324us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 11355.890s 254902.305us 3 3 100.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 287.610s 3908.436us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 325.500s 5537.565us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 287.610s 3908.436us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 679.070s 8186.803us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 679.070s 8186.803us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 483.200s 8154.789us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 416.740s 5545.056us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 755.330s 6413.832us 3 3 100.00
chip_sw_aes_idle 207.630s 2904.868us 3 3 100.00
chip_sw_hmac_enc_idle 192.900s 2398.059us 3 3 100.00
chip_sw_kmac_idle 218.740s 3242.267us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 336.810s 4572.152us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 344.560s 4923.850us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 303.010s 5294.121us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 354.610s 3977.614us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 886.370s 11563.278us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 474.890s 4441.155us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 566.660s 4334.104us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 491.770s 4152.848us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 485.490s 5318.218us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 471.060s 3942.420us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 447.270s 4731.312us 3 3 100.00
chip_sw_ast_clk_outputs 739.450s 7629.526us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 931.110s 11609.500us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 491.770s 4152.848us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 485.490s 5318.218us 3 3 100.00
chip_sw_clkmgr_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 498.410s 4548.050us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 789.800s 6075.928us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4332.880s 18771.643us 3 3 100.00
chip_sw_aes_enc_jitter_en 232.890s 3134.999us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 832.470s 5849.990us 3 3 100.00
chip_sw_hmac_enc_jitter_en 267.310s 3150.576us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1144.420s 9377.843us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 257.880s 3528.143us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 514.340s 5543.662us 3 3 100.00
chip_sw_clkmgr_jitter 199.600s 3090.523us 3 3 100.00
chip_sw_clkmgr_extended_range 33 33 100.00
chip_sw_clkmgr_jitter_reduced_freq 179.890s 2850.927us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 482.820s 5247.168us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 775.730s 7761.635us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4481.570s 25357.911us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 197.940s 3144.865us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 208.680s 2981.500us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1593.640s 12237.481us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 231.390s 3164.963us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 493.110s 6185.527us 3 3 100.00
chip_sw_flash_init_reduced_freq 1467.310s 21306.184us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 20209.720s 180343.729us 3 3 100.00
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 739.450s 7629.526us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 3 3 100.00
chip_sw_clkmgr_sleep_frequency 461.910s 4554.135us 3 3 100.00
chip_sw_clkmgr_reset_frequency 3 3 100.00
chip_sw_clkmgr_reset_frequency 336.320s 2865.752us 3 3 100.00
chip_sw_clkmgr_escalation_reset 96 100 96.00
chip_sw_all_escalation_resets 598.040s 5935.229us 96 100 96.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1151.370s 7902.994us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 1221.640s 7014.669us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 3 33.33
chip_sw_csrng_fuse_en_sw_app_read_test 398.410s 4185.389us 1 3 33.33
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 596.000s 6013.283us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 217.230s 2759.664us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 5885.960s 39208.130us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 210.430s 2532.318us 3 3 100.00
chip_sw_edn_entropy_reqs 916.680s 7274.666us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 210.430s 2532.318us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 1221.640s 7014.669us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 206.520s 3275.623us 3 3 100.00
chip_sw_flash_init 3 3 100.00
chip_sw_flash_init 1575.030s 22793.444us 3 3 100.00
chip_sw_flash_host_access 6 6 100.00
chip_sw_flash_ctrl_access 772.980s 6143.141us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 789.800s 6075.928us 3 3 100.00
chip_sw_flash_ctrl_ops 6 6 100.00
chip_sw_flash_ctrl_ops 533.970s 4040.648us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en 498.410s 4548.050us 3 3 100.00
chip_sw_flash_rma_unlocked 3 3 100.00
chip_sw_flash_rma_unlocked 4671.540s 44355.630us 3 3 100.00
chip_sw_flash_scramble 3 3 100.00
chip_sw_flash_init 1575.030s 22793.444us 3 3 100.00
chip_sw_flash_idle_low_power 3 3 100.00
chip_sw_flash_ctrl_idle_low_power 258.670s 3185.435us 3 3 100.00
chip_sw_flash_keymgr_seeds 3 3 100.00
chip_sw_keymgr_key_derivation 2069.510s 13421.445us 3 3 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 513.830s 6030.472us 3 3 100.00
chip_sw_flash_creator_seed_wipe_on_rma 3 3 100.00
chip_sw_flash_rma_unlocked 4671.540s 44355.630us 3 3 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 513.830s 6030.472us 3 3 100.00
chip_sw_flash_lc_iso_part_sw_rd_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 513.830s 6030.472us 3 3 100.00
chip_sw_flash_lc_iso_part_sw_wr_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 513.830s 6030.472us 3 3 100.00
chip_sw_flash_lc_seed_hw_rd_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 513.830s 6030.472us 3 3 100.00
chip_sw_flash_lc_escalate_en 96 100 96.00
chip_sw_all_escalation_resets 598.040s 5935.229us 96 100 96.00
chip_sw_flash_prim_tl_access 3 3 100.00
chip_prim_tl_access 294.680s 8931.044us 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 718.170s 5277.726us 3 3 100.00
chip_sw_flash_ctrl_escalation_reset 3 3 100.00
chip_sw_flash_crash_alert 556.660s 5684.645us 3 3 100.00
chip_sw_flash_ctrl_write_clear 3 3 100.00
chip_sw_flash_crash_alert 556.660s 5684.645us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 216.540s 3505.507us 3 3 100.00
chip_sw_hmac_enc_jitter_en 267.310s 3150.576us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 192.900s 2398.059us 3 3 100.00
chip_sw_hmac_all_configurations 2 3 66.67
chip_sw_hmac_oneshot 2004.150s 12026.705us 2 3 66.67
chip_sw_hmac_multistream_mode 3 3 100.00
chip_sw_hmac_multistream 1031.420s 5643.993us 3 3 100.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 492.060s 5235.730us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 412.930s 4072.115us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 613.490s 5501.849us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 423.020s 3917.772us 3 3 100.00
chip_sw_keymgr_key_derivation 6 6 100.00
chip_sw_keymgr_key_derivation 2069.510s 13421.445us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1144.420s 9377.843us 3 3 100.00
chip_sw_keymgr_sideload_kmac 3 3 100.00
chip_sw_keymgr_sideload_kmac 2251.390s 12174.942us 3 3 100.00
chip_sw_keymgr_sideload_aes 3 3 100.00
chip_sw_keymgr_sideload_aes 2017.330s 12159.202us 3 3 100.00
chip_sw_keymgr_sideload_otbn 3 3 100.00
chip_sw_keymgr_sideload_otbn 3503.790s 16740.137us 3 3 100.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 244.140s 3114.241us 3 3 100.00
chip_sw_kmac_mode_kmac 263.940s 3027.565us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 257.880s 3528.143us 3 3 100.00
chip_sw_kmac_app_keymgr 3 3 100.00
chip_sw_keymgr_key_derivation 2069.510s 13421.445us 3 3 100.00
chip_sw_kmac_app_lc 15 15 100.00
chip_sw_lc_ctrl_transition 1086.110s 13405.790us 15 15 100.00
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 218.580s 2545.419us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 1839.010s 10319.810us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 218.740s 3242.267us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 530.680s 5533.820us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1080.370s 14638.136us 5 5 100.00
chip_tap_straps_rma 588.060s 8148.939us 5 5 100.00
chip_tap_straps_prod 1439.180s 17880.630us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 215.600s 3193.384us 3 3 100.00
chip_sw_lc_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 1086.110s 13405.790us 15 15 100.00
chip_sw_lc_ctrl_transitions 15 15 100.00
chip_sw_lc_ctrl_transition 1086.110s 13405.790us 15 15 100.00
chip_sw_lc_ctrl_kmac_req 15 15 100.00
chip_sw_lc_ctrl_transition 1086.110s 13405.790us 15 15 100.00
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_key_derivation_prod 1712.710s 11607.642us 3 3 100.00
chip_sw_lc_ctrl_broadcast 78 84 92.86
chip_prim_tl_access 294.680s 8931.044us 3 3 100.00
chip_rv_dm_lc_disabled 220.390s 6985.955us 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 513.830s 6030.472us 3 3 100.00
chip_sw_flash_rma_unlocked 4671.540s 44355.630us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 275.290s 3287.464us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 603.770s 6691.348us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 725.810s 7730.683us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 664.110s 6129.243us 0 3 0.00
chip_sw_lc_ctrl_transition 1086.110s 13405.790us 15 15 100.00
chip_sw_keymgr_key_derivation 2069.510s 13421.445us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 486.860s 9015.714us 3 3 100.00
chip_sw_sram_ctrl_execution_main 767.070s 10070.478us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 931.110s 11609.500us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 474.890s 4441.155us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 566.660s 4334.104us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 491.770s 4152.848us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 485.490s 5318.218us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 471.060s 3942.420us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 447.270s 4731.312us 3 3 100.00
chip_tap_straps_dev 1080.370s 14638.136us 5 5 100.00
chip_tap_straps_rma 588.060s 8148.939us 5 5 100.00
chip_tap_straps_prod 1439.180s 17880.630us 5 5 100.00
chip_lc_scrap 6 6 100.00
chip_sw_lc_ctrl_rma_to_scrap 168.920s 3302.633us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 109.720s 3111.505us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 109.390s 3253.675us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 187.580s 3725.268us 3 3 100.00
chip_lc_test_locked 3 6 50.00
chip_rv_dm_lc_disabled 220.390s 6985.955us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 1857.670s 32926.724us 3 3 100.00
chip_sw_lc_walkthrough 15 15 100.00
chip_sw_lc_walkthrough_dev 5108.680s 47608.657us 3 3 100.00
chip_sw_lc_walkthrough_prod 5294.480s 49156.691us 3 3 100.00
chip_sw_lc_walkthrough_prodend 714.770s 9992.388us 3 3 100.00
chip_sw_lc_walkthrough_rma 5174.940s 47078.472us 3 3 100.00
chip_sw_lc_walkthrough_testunlocks 1857.670s 32926.724us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 9 9 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 95.580s 2450.740us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 98.770s 2634.251us 3 3 100.00
rom_volatile_raw_unlock 101.870s 2453.452us 3 3 100.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 4073.710s 16762.702us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4332.880s 18771.643us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 755.330s 6413.832us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 755.330s 6413.832us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 755.330s 6413.832us 3 3 100.00
chip_sw_otbn_mem_scramble 3 3 100.00
chip_sw_otbn_mem_scramble 401.700s 3826.317us 3 3 100.00
chip_otp_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 1086.110s 13405.790us 15 15 100.00
chip_sw_otp_ctrl_keys 15 15 100.00
chip_sw_flash_init 1575.030s 22793.444us 3 3 100.00
chip_sw_otbn_mem_scramble 401.700s 3826.317us 3 3 100.00
chip_sw_keymgr_key_derivation 2069.510s 13421.445us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 385.460s 4232.536us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 173.680s 3330.608us 3 3 100.00
chip_sw_otp_ctrl_entropy 15 15 100.00
chip_sw_flash_init 1575.030s 22793.444us 3 3 100.00
chip_sw_otbn_mem_scramble 401.700s 3826.317us 3 3 100.00
chip_sw_keymgr_key_derivation 2069.510s 13421.445us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 385.460s 4232.536us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 173.680s 3330.608us 3 3 100.00
chip_sw_otp_ctrl_program 15 15 100.00
chip_sw_lc_ctrl_transition 1086.110s 13405.790us 15 15 100.00
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 456.040s 4967.255us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 215.600s 3193.384us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 27 30 90.00
chip_prim_tl_access 294.680s 8931.044us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 275.290s 3287.464us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 603.770s 6691.348us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 725.810s 7730.683us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 664.110s 6129.243us 0 3 0.00
chip_sw_lc_ctrl_transition 1086.110s 13405.790us 15 15 100.00
chip_sw_otp_prim_tl_access 3 3 100.00
chip_prim_tl_access 294.680s 8931.044us 3 3 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 933.180s 7713.468us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 486.920s 8504.026us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1634.100s 26320.448us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 371.600s 7070.019us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 3 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 474.730s 7661.783us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 595.640s 6349.645us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1425.480s 24423.757us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 6 6 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1286.750s 13610.111us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 679.070s 8186.803us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1013.450s 11757.580us 3 3 100.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 447.780s 4051.560us 3 3 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 486.920s 8504.026us 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 403.040s 4767.636us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 3 33.33
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2290.470s 33434.947us 1 3 33.33
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 429.240s 5619.406us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 405.080s 4815.257us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 3 33.33
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1902.540s 22624.541us 1 3 33.33
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 823.470s 7733.338us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1268.600s 12384.806us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2246.700s 28878.701us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 237.340s 3173.854us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 96 100 96.00
chip_sw_all_escalation_resets 598.040s 5935.229us 96 100 96.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 486.860s 9015.714us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 486.860s 9015.714us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 10 12 83.33
chip_sw_pwrmgr_all_reset_reqs 1268.600s 12384.806us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1902.540s 22624.541us 1 3 33.33
chip_sw_pwrmgr_wdog_reset 447.780s 4051.560us 3 3 100.00
chip_sw_pwrmgr_smoketest 325.500s 5537.565us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 416.800s 5540.366us 3 3 100.00
chip_sw_rstmgr_cpu_info 0 3 0.00
chip_sw_rstmgr_cpu_info 406.570s 4316.211us 0 3 0.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 432.450s 5476.191us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 1353.460s 11852.242us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 229.240s 3178.139us 3 3 100.00
chip_sw_rstmgr_escalation_reset 96 100 96.00
chip_sw_all_escalation_resets 598.040s 5935.229us 96 100 96.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1289.960s 8000.619us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 681.540s 5259.940us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 656.190s 4681.470us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 220.360s 3292.659us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 173.680s 3330.608us 3 3 100.00
chip_sw_rv_core_ibex_fault_dump 0 3 0.00
chip_sw_rstmgr_cpu_info 406.570s 4316.211us 0 3 0.00
chip_sw_rv_core_ibex_double_fault 0 3 0.00
chip_sw_rstmgr_cpu_info 406.570s 4316.211us 0 3 0.00
chip_jtag_csr_rw 3 3 100.00
chip_jtag_csr_rw 1781.370s 18810.308us 3 3 100.00
chip_jtag_mem_access 3 3 100.00
chip_jtag_mem_access 1083.590s 14137.671us 3 3 100.00
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 416.800s 5540.366us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 252.170s 2869.484us 0 3 0.00
chip_rv_dm_access_after_wakeup 3 3 100.00
chip_sw_rv_dm_access_after_wakeup 349.990s 5899.802us 3 3 100.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 588.060s 8148.939us 5 5 100.00
chip_rv_dm_lc_disabled 0 3 0.00
chip_rv_dm_lc_disabled 220.390s 6985.955us 0 3 0.00
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 720.110s 5267.768us 3 3 100.00
chip_plic_all_irqs_10 338.530s 3311.106us 3 3 100.00
chip_plic_all_irqs_20 446.010s 4065.461us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 205.140s 2475.918us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 243.230s 2888.531us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 3545.850s 14124.864us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 581.090s 7060.961us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 231.760s 2999.762us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 302.660s 3353.169us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 221.950s 2560.766us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 385.460s 4232.536us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 514.340s 5543.662us 3 3 100.00
chip_sw_sleep_sram_ret_contents 6 6 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 612.580s 8164.686us 3 3 100.00
chip_sw_sleep_sram_ret_contents_scramble 659.630s 7946.755us 3 3 100.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 767.070s 10070.478us 3 3 100.00
chip_sw_sram_lc_escalation 102 106 96.23
chip_sw_all_escalation_resets 598.040s 5935.229us 96 100 96.00
chip_sw_data_integrity_escalation 622.920s 6889.796us 6 6 100.00
chip_sw_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 823.470s 7733.338us 3 3 100.00
chip_sw_sysrst_ctrl_reset 1264.400s 21383.760us 3 3 100.00
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 211.760s 3083.209us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 3 3 100.00
chip_sw_sysrst_ctrl_outputs 296.160s 3662.023us 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 445.920s 4703.381us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 3 3 100.00
chip_sw_sysrst_ctrl_reset 1264.400s 21383.760us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_reset 3 3 100.00
chip_sw_sysrst_ctrl_reset 1264.400s 21383.760us 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 3 33.33
chip_sw_sysrst_ctrl_ec_rst_l 2966.090s 20488.531us 1 3 33.33
chip_sw_sysrst_ctrl_flash_wp_l 1 3 33.33
chip_sw_sysrst_ctrl_ec_rst_l 2966.090s 20488.531us 1 3 33.33
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 487.610s 6578.558us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3445.510s 34964.350us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 238.130s 2758.427us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 204.680s 3022.488us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 417.480s 3934.646us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 380.440s 4522.928us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1484.620s 8803.939us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 6814.690s 31882.515us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2281.520s 11574.556us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 160.100s 2583.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 234.650s 3359.819us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 3 33.33
chip_sw_rv_core_ibex_lockstep_glitch 223.360s 2728.338us 1 3 33.33
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 14908.550s 71988.806us 1 1 100.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 1306.330s 6821.457us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 705.140s 13472.859us 0 1 0.00
rom_e2e_jtag_debug_dev 465.730s 4799.668us 0 1 0.00
rom_e2e_jtag_debug_rma 449.000s 5384.780us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 93.760s 2631.739us 0 1 0.00
rom_e2e_jtag_inject_dev 92.060s 2547.010us 0 1 0.00
rom_e2e_jtag_inject_rma 79.960s 2369.207us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 17.793s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 3 3 100.00
chip_sw_clkmgr_jitter_frequency 694.920s 5004.309us 3 3 100.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 351.900s 2546.907us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1260.250s 7170.719us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 1282.660s 8076.360us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 313.810s 2861.225us 3 3 100.00
chip_sw_flash_memory_protection 3 3 100.00
chip_sw_flash_ctrl_mem_protection 717.420s 5371.584us 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 206.810s 3239.742us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 178.600s 3396.531us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 2 3 66.67
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 414.670s 5361.936us 2 3 66.67
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 386.020s 5231.257us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1268.600s 12384.806us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 705.140s 13472.859us 0 1 0.00
rom_e2e_jtag_debug_dev 465.730s 4799.668us 0 1 0.00
rom_e2e_jtag_debug_rma 449.000s 5384.780us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 3 3 100.00
chip_sw_rv_dm_access_after_escalation_reset 485.070s 4966.891us 3 3 100.00
chip_sw_plic_alerts 96 100 96.00
chip_sw_all_escalation_resets 598.040s 5935.229us 96 100 96.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 0.000s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 0.000s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 3 3 100.00
chip_sw_spi_device_pinmux_sleep_retention 229.680s 3610.288us 3 3 100.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 494.390s 4426.943us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3978.320s 18767.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 17 22 77.27
chip_sival_flash_info_access 256.520s 3137.566us 3 3 100.00
chip_sw_rstmgr_rst_cnsty_escalation 568.590s 4871.890us 3 3 100.00
chip_sw_otp_ctrl_rot_auth_config 77.520s 2387.225us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 166.300s 2616.480us 3 3 100.00
chip_sw_otp_ctrl_descrambling 263.490s 3164.683us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 311.730s 2934.216us 2 3 66.67
chip_sw_pwrmgr_sleep_wake_5_bug 18.324s 0.000us 0 3 0.00
chip_sw_flash_ctrl_write_clear 260.830s 3299.243us 3 3 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31644) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 61847555097980152490714956539730963365052715697278682585364101359948066911459 214
UVM_ERROR @ 2684.570504 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31644) { a_addr: 'h106b0 a_data: 'h1da6aa24 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h19268 d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2684.570504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 113179076033238029091337015715886060877594960094964361198848640575122133547885 232
UVM_ERROR @ 5375.645718 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x107c4 read out mismatch
UVM_INFO @ 5375.645718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 50244316308506452800233708184853314508823558078154811483966708825720681718953 242
UVM_ERROR @ 6985.955142 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x106fc read out mismatch
UVM_INFO @ 6985.955142 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 13188310378729895864488008272833452150087854014414154331375748880640750135844 223
UVM_ERROR @ 4562.517150 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105a8 read out mismatch
UVM_INFO @ 4562.517150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36934) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 3585206064674635806868000239341320852585205041746061451182494944319287341404 214
UVM_ERROR @ 2012.655273 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36934) { a_addr: 'h1042c a_data: 'hcb21d5ba a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h19530 d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2012.655273 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@216806) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 109971093554391670969183351658520731724005313781552252871454820002646237541722 239
UVM_ERROR @ 6375.738024 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@216806) { a_addr: 'h107e4 a_data: 'h8c4aa4d8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h4 a_user: 'h195d3 d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 6375.738024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37754) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 86897502125054718572175445967647522258448302163388732539559908295944303226624 214
UVM_ERROR @ 2307.106576 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37754) { a_addr: 'h1076c a_data: 'h3e61779f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h1b18b d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2307.106576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32832) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 100843073411036695262717899152538985554740370929447589617287522984432232802475 221
UVM_ERROR @ 2375.393210 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32832) { a_addr: 'h10784 a_data: 'hcbde6414 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf a_opcode: 'h4 a_user: 'h1a5d4 d_param: 'h0 d_source: 'hf d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2375.393210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34582) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 95188714899253789024812671864918376778675438568194862528652194950850691315852 214
UVM_ERROR @ 2803.989580 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34582) { a_addr: 'h10384 a_data: 'h43ef59ba a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h4 a_user: 'h1b689 d_param: 'h0 d_source: 'h28 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2803.989580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31636) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 35865179405417710101237533542084472845179186845545069531297124235831461154082 221
UVM_ERROR @ 2217.642205 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31636) { a_addr: 'h10694 a_data: 'h13c1641d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h10 a_opcode: 'h4 a_user: 'h18647 d_param: 'h0 d_source: 'h10 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2217.642205 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32278) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 31554713419204738077229589971768319663411877035151908584240888884723222836794 214
UVM_ERROR @ 2139.703388 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32278) { a_addr: 'h1067c a_data: 'hb1cd616a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h19229 d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2139.703388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31868) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 8296536899829918056352018380393090890672592065809995611823718456236943108191 214
UVM_ERROR @ 2346.495384 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31868) { a_addr: 'h106d8 a_data: 'h51cbfeaf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h37 a_opcode: 'h4 a_user: 'h1b69b d_param: 'h0 d_source: 'h37 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2346.495384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32582) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 102590968144204428626797920379577885847032904943532619066903015204500219855895 214
UVM_ERROR @ 1959.230600 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32582) { a_addr: 'h104d4 a_data: 'h5faf5159 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h1a5c1 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1959.230600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31592) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 70473369177589520505157076833386340466334458157914141239076558067270097971541 221
UVM_ERROR @ 2483.885020 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31592) { a_addr: 'h107bc a_data: 'h8f0dd17a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h18d27 d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2483.885020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32784) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 61385642669046240207346254152533908512049651369810296330574495162620495800488 214
UVM_ERROR @ 2496.141087 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32784) { a_addr: 'h10648 a_data: 'he128f80c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h1a294 d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2496.141087 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31988) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 97165286635099839741229507492842377077208364545922932930078522760853895812058 214
UVM_ERROR @ 2113.696092 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31988) { a_addr: 'h10614 a_data: 'h868f1015 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h4 a_user: 'h1b6dd d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2113.696092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32880) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 109074387540280992781247354654562737624134893307392931419867247366939634999702 214
UVM_ERROR @ 1762.357716 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32880) { a_addr: 'h10618 a_data: 'h385b2d38 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7 a_opcode: 'h4 a_user: 'h1aea7 d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1762.357716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31632) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 74812324834918847242814958421276804941429482760478068240147975337977029204603 221
UVM_ERROR @ 2849.245892 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31632) { a_addr: 'h105c4 a_data: 'hc5ec5e4a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h4 a_user: 'h18621 d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2849.245892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36526) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 67745774448704155643911015474090816940756856804699247061038492807969292356710 214
UVM_ERROR @ 2401.115316 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36526) { a_addr: 'h107d4 a_data: 'h986bf547 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h1a99a d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2401.115316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36630) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 84388542734303378452805943983292175990890662209331980828742492453512260897916 223
UVM_ERROR @ 2703.280964 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36630) { a_addr: 'h60c a_data: 'ha4adbf79 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h1 a_user: 'h26c87 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2703.280964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37328) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 5711554918567927883501525969861653843822276540043008914106185056458907341314 214
UVM_ERROR @ 2397.262169 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37328) { a_addr: 'h105f8 a_data: 'h5f070203 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h4 a_user: 'h1a24f d_param: 'h0 d_source: 'h11 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2397.262169 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31700) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 112175537851399479744536037238465785474389819514353529393978056573821402762811 221
UVM_ERROR @ 1823.052454 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31700) { a_addr: 'h10780 a_data: 'hc486f05f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h1a976 d_param: 'h0 d_source: 'h18 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1823.052454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34926) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 81094399564244354561716964229876425648298247800076827888728696474641224159663 214
UVM_ERROR @ 2461.774212 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34926) { a_addr: 'h105d4 a_data: 'ha84d5916 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h38 a_opcode: 'h4 a_user: 'h1a282 d_param: 'h0 d_source: 'h38 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2461.774212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31768) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 55514899287279074655675605919416321910189370561957290671936082565372355082395 221
UVM_ERROR @ 2528.193495 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31768) { a_addr: 'h104a4 a_data: 'hc2f8bf83 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3b a_opcode: 'h4 a_user: 'h1b10e d_param: 'h0 d_source: 'h3b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2528.193495 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@111470) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 66283240231473542393752953247792712898245464752595508818765499299569798973206 215
UVM_ERROR @ 3188.170418 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@111470) { a_addr: 'h10570 a_data: 'hb640ce18 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h18666 d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3188.170418 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@188406) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 74765801507459218479710919533454070032673681577554183191311403152718998762613 215
UVM_ERROR @ 3402.324152 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@188406) { a_addr: 'h10784 a_data: 'he6dfcf98 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h1a5d3 d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3402.324152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31576) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 114132498284769039635509068277263977662945965785034576599230482766402016990606 221
UVM_ERROR @ 1996.717990 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31576) { a_addr: 'h1052c a_data: 'hed1da871 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1f a_opcode: 'h4 a_user: 'h19274 d_param: 'h0 d_source: 'h1f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1996.717990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32560) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 42477946518013521007038367459802174934268500387784254016091821148207181356784 214
UVM_ERROR @ 2484.212400 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32560) { a_addr: 'h10450 a_data: 'hcd8b904a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h1999c d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2484.212400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31626) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 105679318209211118117054524931063118074447953282519267779264902427475059528289 221
UVM_ERROR @ 2257.611225 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31626) { a_addr: 'h10730 a_data: 'hcb749c40 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h1a596 d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2257.611225 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31624) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 19498176932495769669206191217417177274931373391129860715762775793090612960906 214
UVM_ERROR @ 1711.652364 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31624) { a_addr: 'h10764 a_data: 'hbc697cbf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h1a509 d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1711.652364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34446) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 80070299880723596812057227255934589182689379429423237898301837122796170488141 214
UVM_ERROR @ 1835.512937 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34446) { a_addr: 'h10110 a_data: 'h80ae50b0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2d a_opcode: 'h4 a_user: 'h1a536 d_param: 'h0 d_source: 'h2d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1835.512937 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@130988) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 76129311106310112103069591907707180486009161089451875922307226541983389816545 215
UVM_ERROR @ 3009.910264 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@130988) { a_addr: 'h104dc a_data: 'h52ab98d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1a a_opcode: 'h4 a_user: 'h1b129 d_param: 'h0 d_source: 'h1a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3009.910264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32136) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 29003371567343056788179530561115734611596879827166831340383085793770740058090 221
UVM_ERROR @ 2233.192984 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32136) { a_addr: 'h10110 a_data: 'h2b918ba0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h1a518 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2233.192984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32338) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 102574767936917456184718038522590599089798548493794182642673254610165790868482 214
UVM_ERROR @ 1893.382108 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32338) { a_addr: 'h105e8 a_data: 'h371b9c8d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb a_opcode: 'h4 a_user: 'h186b0 d_param: 'h0 d_source: 'hb d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1893.382108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37048) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 74631315976074255484646490931767139696085570151986381194779974360649544572334 214
UVM_ERROR @ 2313.862488 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37048) { a_addr: 'h10714 a_data: 'h1a2a903f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1b1f3 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2313.862488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32114) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 39632099733178681149712198528087721303679474191409918157321830653431785443841 214
UVM_ERROR @ 2476.419656 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32114) { a_addr: 'h106c4 a_data: 'h5c670c9c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h18a3c d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2476.419656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32972) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 86116806470254645367500361966948144467658084413033941082472000666587023712755 214
UVM_ERROR @ 2575.907060 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32972) { a_addr: 'h10688 a_data: 'h985f8dec a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h1bad2 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2575.907060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33044) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 42688088647802921187588914015306394963587607197555296953864008332784078328853 214
UVM_ERROR @ 1870.198625 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33044) { a_addr: 'h105d4 a_data: 'h5c9deff5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h4 a_user: 'h1a2aa d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1870.198625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31912) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 110431421699809526914098012343005637687435865383294825249033632775001292628842 214
UVM_ERROR @ 2619.918980 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31912) { a_addr: 'h10684 a_data: 'h94503291 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h1a2b0 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2619.918980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38230) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 111196124176208876983167173149077488230405881669408181458071481701395250943695 214
UVM_ERROR @ 2377.735075 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38230) { a_addr: 'h10550 a_data: 'h4bc60149 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h19ecf d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2377.735075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32188) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 73734630839718052743028849418834695515963549204478047123729132643354647851157 214
UVM_ERROR @ 2069.356658 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32188) { a_addr: 'h10770 a_data: 'hc6e3d0a3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h18d2f d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2069.356658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 104708297980567462962998431240563087504955707943472815001552878598162371672208 406
UVM_ERROR @ 3295.752305 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3295.752305 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 95621207950472117023606031418727213174820812431627816299857170261000744208521 402
UVM_ERROR @ 3309.777289 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3309.777289 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 66812882640284999802431178448610050595961738080371426903987289865238153877792 402
UVM_ERROR @ 2999.761500 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 2999.761500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 97227545942077014912755657227775562343661214456744097431113365037077243517475 433
UVM_ERROR @ 6129.242697 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 6129.242697 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 92542803166150524526077996131387809179039099884587126542187786084711731844567 423
UVM_ERROR @ 5480.920640 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 5480.920640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 85834918770583218544598260969276169583330442101380895651316103037510964337404 422
UVM_ERROR @ 7647.850694 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7647.850694 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 4216916228004134056590375825650942559637201345733058246081803055897111912007 398
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3396.530808 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3396.530808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 41706158673183334510033992104513429628686363554229726531753676126769340696030 394
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2589.924776 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2589.924776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 3775556917444795476666828421425900942800061691259111737405507290329500353066 398
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3613.983592 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3613.983592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 91400358714687847016981138558985951044983267130443261690939482143472506040073 401
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3017.683508 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3017.683508 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_otp_ctrl_rot_auth_config 33988557400720190241053553290424161529833492467674047533910707800992045452898 417
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 31591843625880022616064484448124476825144453947218923529138685984795123904637 413
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 79052408943045258252658458248121916347452102525322483152821245043058337183485 533
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 69093975955401578517504231319988710530447486273405062066503957985258157729239 518
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 55285238609055942050194710665227831181465282160126475897613021197338812245861 483
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 77051013977506870930758410086801349820561911748402792162717060983818386832460 452
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 21923856340915720542803003932576411141736031684672271725933930409363004551934 458
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 32620109875619760342896261270301758447204728511815564538243578783863062650488 409
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 38181376535172469090670710169092890622534654867429901634429497989240433754008 412
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@88852) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 7482764193976100828213685232484519330280404340898968999723188136303226264781 421
UVM_ERROR @ 3795.624328 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@88852) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3795.624328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 11824678654031993200633457076942031877525761078663443613429077289734654277725 430
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 13091.739000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13091.739000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 39654264975926637983448690509774075738582000648224958168000762636502773582805 416
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6582.187500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6582.187500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 36216562311642127355907668476527994157835632810289816724507872901429591612326 447
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 18015.158500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 18015.158500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 53815686152584330381577393026950513716893168745355348076432904652544592657920 397
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6294.654000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6294.654000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 84680192002415391678417848801319283851175401717400958841469704729337055574602 406
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 8440.392000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8440.392000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 32586756691200510951798832105433726042736213036344009417977379028302568962000 453
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 19401.581000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 19401.581000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 71510083675372271507421230596269322810137339950302553566138661561004574350862 405
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7661.783000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7661.783000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_rv_timer_systick_test 61270259588654380459551165376746888166068218890472023135157089762482649251626 None
Job timed out after 120 minutes
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 89067757764469826668159855783444497333745698219600173360565510219151352143572 None
Job timed out after 60 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 87154594019898311519873345351185824324497089821224595282360646198916076642859 None
Job timed out after 240 minutes
chip_sw_rv_timer_systick_test 109911193020882621182510443729375789471408989851371283652269740163581299266467 None
Job timed out after 120 minutes
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 25717062814940342483312263811527545777960089645946472606720111858914400600734 None
Job timed out after 60 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 91465985122034349435292498692448832107850061905465181911357226120429891042859 None
Job timed out after 240 minutes
chip_sw_rv_timer_systick_test 74150337537328844899753361021520868201670091571804229518796797040758811652041 None
Job timed out after 120 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 62455057193246414671970100551622414002006021501366236460082361744436648214859 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert *!
chip_sw_alert_test 75762319163537127123148063739429095507833397081985486321159195145277240503521 390
UVM_ERROR @ 2946.141176 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert 31!
UVM_INFO @ 2946.141176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 25171308450025574266822445122370501170962526421950903163484151387168389756477 386
UVM_ERROR @ 2680.636325 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2680.636325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85809914649705950049059180893428367081455206714019068388710244694810164546167 390
UVM_ERROR @ 2121.902900 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2121.902900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6589578824553717908827220633593383176222224857017528051379801826902929865729 389
UVM_ERROR @ 2608.622200 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2608.622200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 74821811231105135054925891757450766238691373553312782019876510622946262611173 390
UVM_ERROR @ 2711.544177 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2711.544177 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 4725573749456915602040880781161141906354820249536030128628373713863872499864 385
UVM_ERROR @ 2459.794567 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2459.794567 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79703923315180168333397567571349421725211154310139094852761547478939102415060 390
UVM_ERROR @ 3420.231674 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3420.231674 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 29554905723324773432020690326940296808018795237075941072495219568859401955348 395
UVM_ERROR @ 1966.908760 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 1966.908760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46923369254353372421695744225931774810006745386566441526351327785890645927299 390
UVM_ERROR @ 2821.614497 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2821.614497 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 59429702284744894592498395737952292721356514097766378963391192852509069578203 390
UVM_ERROR @ 3006.189368 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3006.189368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35139419283924124313878152738145520569740383707674337220541527662497935421074 390
UVM_ERROR @ 3111.221556 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3111.221556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 98701961423326340773089390321352424202131710972523155371554903402149476809439 397
UVM_ERROR @ 2969.390262 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2969.390262 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 76225552713030640962920490394593192112887835766480951132347519992749562763503 398
UVM_ERROR @ 2767.852552 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2767.852552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42694617449201380495924667947390566258858334264498063164249743567478961794337 393
UVM_ERROR @ 3132.211635 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3132.211635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34108955219173506883318048905365226157695244958252921492358818854456625949697 390
UVM_ERROR @ 2597.231210 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2597.231210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 61299229407347994083226326731860681379867284723268117184452379200938670296440 390
UVM_ERROR @ 2962.733672 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2962.733672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 24524257225215016859791751807809262070450498633659708469474110366978410135981 390
UVM_ERROR @ 3423.435812 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3423.435812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 44846051379715118419273639686535917410766427414144292454460542955241921098737 392
UVM_ERROR @ 3511.092792 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3511.092792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 17274231147721769050661421838547977266404968356358336093980098407898121378765 392
UVM_ERROR @ 3410.042064 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3410.042064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 83211772050769290221973124284448557256374695779650499566574938445971414766029 390
UVM_ERROR @ 2246.662860 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2246.662860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 67283685182398844763406233877284358931348525045965489707160339286249916656054 390
UVM_ERROR @ 2725.957769 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2725.957769 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 29320524089542064693729965213723393704024390130219027352571223543270525229121 390
UVM_ERROR @ 2994.940101 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2994.940101 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 100491390257952333359261613290282342353674991044312188244332582719036134467349 397
UVM_ERROR @ 2978.623192 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2978.623192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109851231282556719680345470111551867877282347918317338140702205820835520533653 390
UVM_ERROR @ 3070.765428 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3070.765428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 31346308002338972014282333265235464392340968260732658293698762985931502587798 395
UVM_ERROR @ 3389.490252 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3389.490252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 45578687721009835457715672846607309887759582091819542969217087365931905683968 390
UVM_ERROR @ 3365.563212 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3365.563212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 74041962223674412565655502158009957118883597446573386164269008548743341266533 390
UVM_ERROR @ 2773.519025 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2773.519025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 7269693384316448590575564097961190873694394185391896863056359194147960373518 389
UVM_ERROR @ 2808.695296 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2808.695296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107042957658385626157590342901624641263301825930496240028433123928753005676124 399
UVM_ERROR @ 2499.269432 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2499.269432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 89096094966211769882073701243796218629867320622884231157442379132121034726454 390
UVM_ERROR @ 2900.287672 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2900.287672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 53144115553968525440162238497237607302396716306704706838888160462358016532896 390
UVM_ERROR @ 2309.510815 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2309.510815 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46261701610176261037412146745346178357292794052935023333345844909918013454807 390
UVM_ERROR @ 2817.781021 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2817.781021 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101443590055455853894711719506872712136580526165909708913105194093474544881014 390
UVM_ERROR @ 2363.885342 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2363.885342 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 112105014002135320703718815935854141135319313641815076095004822724193538774225 390
UVM_ERROR @ 2158.306100 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2158.306100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42489508012636643679898094817533551467367796508745120154209455489794622012080 393
UVM_ERROR @ 3059.654964 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3059.654964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96999686316835267259595207631884142515808394922732646986560129360067955602933 398
UVM_ERROR @ 3040.950296 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3040.950296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 94871775039343364372255787358789626514576172183591770468122549076692122238357 389
UVM_ERROR @ 2171.774094 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2171.774094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 53996197404175857452039003401132607939282066543054508017734071205004266496675 390
UVM_ERROR @ 2569.347924 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2569.347924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 56441623613205494263576033413350000200484568662468408628789694769264768282936 390
UVM_ERROR @ 2415.594590 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2415.594590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 98999274615932411916308652845431706843101297778416143212075665478703906692595 395
UVM_ERROR @ 2861.458590 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2861.458590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 295724313226096101500919888611155301754811064149018373175315664744217280678 394
UVM_ERROR @ 2473.330396 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2473.330396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 17628039390363813070632092931038852859147524195656882503561958169084063452699 385
UVM_ERROR @ 3163.614628 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3163.614628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84987804198396082484674834307784283130420632281795210491042600151438222005939 390
UVM_ERROR @ 3334.970770 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3334.970770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 45946842426689879314846641854040171484805221714369593311903783667751652837083 385
UVM_ERROR @ 2115.248197 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2115.248197 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71915703121100144562677668036793310075213300936196168494712704985077054150696 390
UVM_ERROR @ 2698.422586 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2698.422586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85394901608431800341485391979366110194422498262750072963798692760650779084680 390
UVM_ERROR @ 2858.992661 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2858.992661 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102607173419352964202373242626372327544460519917650808696647587069711191496865 390
UVM_ERROR @ 2472.120500 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2472.120500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84786848958802130266109777756267696139903146224188067447706885904192855045937 392
UVM_ERROR @ 3042.495910 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3042.495910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34962623411108775593300724103398003762415437636520995311440794606005785014809 397
UVM_ERROR @ 2924.648205 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2924.648205 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102758838661599632132289469825185892484507543347932146509381514865795743477174 393
UVM_ERROR @ 3161.797548 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3161.797548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88596657199766596449695394716276476376443390441799622909736545019680581226253 390
UVM_ERROR @ 3419.555768 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3419.555768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 90515010181159240527708979444162919828724703948486523837565503996383835190900 399
UVM_ERROR @ 3011.386422 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3011.386422 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 104511544936585848349707385521146291454707550775916436417540197013561652615415 393
UVM_ERROR @ 2530.726104 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2530.726104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 75874032262216093195903737079360261020538854177807280673809395948779773697396 400
UVM_ERROR @ 2916.417534 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2916.417534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 10886286006179272556031733500467268538523210929606464184515643254343313985119 395
UVM_ERROR @ 3599.469831 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3599.469831 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 41946233393252039305873630754671421635702019501509147692271811634575050920340 395
UVM_ERROR @ 3265.057244 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3265.057244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 47917868975242493287679893315188265793362774879345823471183496987844544907456 390
UVM_ERROR @ 2713.079540 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2713.079540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 13890685137892683075975956905282958790157244387095553641413657665861112875853 394
UVM_ERROR @ 2398.254598 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2398.254598 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 82887849671566856916945063735490026146225462555006346183630708650209061163950 394
UVM_ERROR @ 3127.887380 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3127.887380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 67611459210692040475416821602899887642057043980419834121038214018608399487700 389
UVM_ERROR @ 2229.449139 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2229.449139 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 44348721968113716163052997147015060149949854444994301226574310858067027381839 393
UVM_ERROR @ 2670.954660 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2670.954660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 110906317610354793518041501213755198579340138414778873875915841520331686336948 397
UVM_ERROR @ 2931.577560 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2931.577560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101074840031208344400299142836924115105804494335752665500608995541861271003647 389
UVM_ERROR @ 3008.987116 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3008.987116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 89642906584559097441455069670233123222756988297828028069037922033879430138710 397
UVM_ERROR @ 2977.595950 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2977.595950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81954751644542759865221111220002630139503834403605986508372412277868795832352 399
UVM_ERROR @ 3125.176144 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3125.176144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 114464749947225941586347127113884828521861363139635656883194997236412228264633 386
UVM_ERROR @ 2839.273375 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2839.273375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 115218731139137105978825597708890801554786855194729240666569819633459526793092 397
UVM_ERROR @ 2722.680000 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2722.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 110021207764261924854623278363621273125460118455757872444030306513093565733625 399
UVM_ERROR @ 2822.626959 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2822.626959 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 92242031259800045315260453262479582484794398922938651693316027959915446863995 389
UVM_ERROR @ 2958.806832 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2958.806832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 100828431700530119485114846214173659741281148509910484825131522388625216270498 396
UVM_ERROR @ 2822.467282 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2822.467282 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 100212519047832353104099180637707612643627118127380296159149485690095350358798 390
UVM_ERROR @ 2646.828022 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2646.828022 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 87460056414689074971620454243083414420625455532811701206351280957071805905792 399
UVM_ERROR @ 2639.147536 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2639.147536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101053480596926490463140142823854313307847315933864910142831028132171971767668 397
UVM_ERROR @ 2123.374500 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2123.374500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 89195708087960931369271226577981328892159628608370607186468313016189949701167 392
UVM_ERROR @ 2534.540271 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2534.540271 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 58489032349487840300482412480711866850536543661980168683794254875660164545944 393
UVM_ERROR @ 2767.555259 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2767.555259 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 22393773528641523159515116318308226247129613169206483946017220127973300120081 396
UVM_ERROR @ 2817.912061 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2817.912061 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 5647424020023054158311138709858430909148556866589044589173478404450318089978 397
UVM_ERROR @ 2921.814933 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2921.814933 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 44807967082950969688305730091579142535591824048238156342812824083682610034752 395
UVM_ERROR @ 2676.796350 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2676.796350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 114479067910788083936549359541854444069360938536512403734792762431402092159122 397
UVM_ERROR @ 3105.300934 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3105.300934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 94499739716247816861079100735720728998677954931847204312986350949805961887030 390
UVM_ERROR @ 3081.568585 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3081.568585 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 70003844274385660476456114621579403948972093346094868961801599589940057048596 396
UVM_ERROR @ 2356.696618 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2356.696618 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 5393147015855412684224832975492338990344478748342249880780714049417563986627 394
UVM_ERROR @ 2490.252392 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2490.252392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 59830215198805327818070794932301950154460235440899455878914040604194399108880 410
UVM_ERROR @ 2512.748625 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2512.748625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62480665777623198020781554079200012174160609154475704832989970172897725618047 412
UVM_ERROR @ 3141.787656 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3141.787656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 69112849489480680439577656127151106677125253574611800773165393499005033211924 396
UVM_ERROR @ 2701.273126 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2701.273126 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101892050875494310816156729139781485341272930573815788832927222337566456778482 390
UVM_ERROR @ 2549.975888 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2549.975888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14644793118417891092464745208017981349854483799716140846549069415851471310340 395
UVM_ERROR @ 2590.710432 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2590.710432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81847903885927777367998140496789815936227737667998490865002010377629506503643 390
UVM_ERROR @ 3150.643251 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3150.643251 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71538198320646950643615997129427327317140032608577835594747159361056769912870 396
UVM_ERROR @ 2313.081666 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2313.081666 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62323331442046189856985462512285316589349863635709613604475958579293430291096 390
UVM_ERROR @ 3052.199184 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3052.199184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 70719425110926675333760209788117415165604867150614641040402511730229135128858 393
UVM_ERROR @ 2876.928135 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2876.928135 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 31030870953016593075260148195498630451107943161542390057534834206111083538249 394
UVM_ERROR @ 2503.629275 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 2503.629275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 98592533950389511729229932331476373103209046702267165589924896155774351896647 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 4.924s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 99388760857875891537168468690314811191733150911870593716952148526098675007637 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 6.111s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 65081703649847682915696398450140941209898966726882646931760097592724678589473 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.869s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 65553010839108305194831750785241290450087822709879766329679590525501421311600 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.211s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 1482985740911149413954446292252266159717048915816323363323927222880556696443 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.222s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 100183814714755201118877580799412614616170452658780298131465810423790459701075 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.218s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 58144589556765803445633904629428373931569774224575129122187081465266436329779 404
UVM_ERROR @ 3432.658000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3432.658000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 110661216816942857112444260186491505304367925923193763751505378504266211199584 395
UVM_ERROR @ 3358.015500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3358.015500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 108129300200415902891972998921870152359313476861331836139693259495079663040101 416
UVM_ERROR @ 3246.507000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3246.507000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 36927729007588846275875516010551179925274870342992687807356816202429888648817 405
UVM_ERROR @ 3701.724000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3701.724000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 77903276650456843865792953116042597698373155638163917175291222430489275319619 408
UVM_ERROR @ 3253.488000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3253.488000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 81897441693097857396083165971560413895842238194348764302084902188835806550998 415
UVM_ERROR @ 3347.781000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3347.781000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
chip_sw_ast_clk_rst_inputs 12618489608269800378146497753473321141754079773035073760074447763403714821829 415
UVM_ERROR @ 19430.934055 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 19430.934055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 108867787031422901452543970052151208151424027495285596375455955787066649744477 414
UVM_ERROR @ 16206.130855 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 16206.130855 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 45628684071403675539865696335966632919994638566360757279116313667433220095714 432
UVM_ERROR @ 21175.335092 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 21175.335092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 104909641968745402445609156534184430232464371504042149840566432405249528993135 489
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 53776181411469635525402650256391013467845659819159830296146709161854062722344 484
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 55630532536808651390622207739855648011602796465501485912727261088928587139853 478
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 88206936929427615200558022754282834593899016117714119953317348839423321939737 583
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 24017959362409129146305751381255968368890640253236956859890296539886043112910 564
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 98614835692466884864978888149197993068575373506738611158901516365581081854555 710
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 110872395948398556957544918699538505290015451776542097198479178770268850116461 635
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 50307021849427335633985579211865890807511557919971719196983152596310257273683 603
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 31425696114999509185340087810579348037844501862428264496035413409863114258792 657
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 101281929377929177777314825726813741780068642746325909317679658065203062667502 596
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 2767982359235558904002992094763699197026020285479115286562073797832015580141 789
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 65542584679165315537249736040784477990099737543328851405784801369924582996912 743
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 103011334880605811921676017395182572307727610621584131508062055718147436101478 775
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 5293628243830103004644279365175911652942782674736709556159342928585548095268 612
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 56122053416759361466452060396273734908477244473951175343893787397994621038801 690
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 104041898484346589566876583875028584962961034046604960369457187871938505908024 668
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 110104056331359426993668577371630857671655108683881469556138143455812489225314 660
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 657063320510224350906902509525603206608909050120122980359854920651309765040 606
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 16345354244969911799002114525491939332221323228170091800467448606142037152480 697
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 50162845596031090227603129648488988952795047110593132726248305182066558384220 534
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 110597068757266000870767310059496622165345199179226400209063805048957688409535 512
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 52386933618326621718735913245418380242685051615758651081067553873786277307915 655
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 98893031712065641021616914623853049245295885258334054152309446470348625571058 654
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 30298146200266380326633646443862803133621815874076432177730692708366608935921 657
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 12613529527534240794655963641766843418950604468437558395971714659641272789054 630
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
rom_e2e_jtag_debug_test_unlocked0 23211540936113722363419954572552750916895451654053762831079345729162430275266 534
UVM_FATAL @ 13472.859125 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 13472.859125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got *
chip_sw_all_escalation_resets 100976803040625708015545714801764559429094357899183179843410029850957350199402 399
UVM_ERROR @ 2847.134460 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2847.134460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 68738351841605233636574236973051833903512941502868062849296725049127416148855 535
UVM_ERROR @ 3252.159000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 3252.159000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@114196) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 20695687912427580867740288395847348061055726409635130437853008160548858686002 414
UVM_ERROR @ 4316.211350 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@114196) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4316.211350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
chip_sw_sysrst_ctrl_ec_rst_l 99085827312950878136356082808151093391778913492966077090938572426066384374431 401
UVM_ERROR @ 11736.627132 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
UVM_INFO @ 11736.627132 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_ec_rst_l 104595515773709059245132156142376983997376048839171284264983804327443080723036 406
UVM_ERROR @ 12250.201431 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
UVM_INFO @ 12250.201431 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 66039907485464049029352412830726944338125683159140376726526633477672586682835 389
UVM_ERROR @ 2639.989644 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
UVM_INFO @ 2639.989644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_test 4006958795661625577061000847761772548810409740233634935821729891182430529646 389
UVM_ERROR @ 2742.687450 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
UVM_INFO @ 2742.687450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reset_cause == HwReq)'
chip_sw_sensor_ctrl_alert 114890636169002972490075999502642772448729560074692388897425835903090686162058 400
Offending '(reset_cause == HwReq)'
UVM_ERROR @ 2727.035934 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2727.035934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sensor_ctrl_alert 99911295483743418578382785026109079210894034621133101425528212281965795826565 426
Offending '(reset_cause == HwReq)'
UVM_ERROR @ 5924.508712 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 5924.508712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 32332916127516833098876999832479579659297646023855171565956148380045734926887 407
UVM_FATAL @ 2728.338192 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2728.338192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_core_ibex_lockstep_glitch 42952803490681019897750233877380014942695379665765953893042040675945472317583 408
UVM_FATAL @ 3062.977580 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 3062.977580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 80885823160839902367819744318044781663123987730216317710880551342888392910741 426
UVM_ERROR @ 17315.268525 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 17315.268525 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(pin_wkup_req_o))'
chip_sw_sleep_pin_wake 111273651678024152469530791365228881835620444963054698359146916135978980956723 400
Offending '(!$isunknown(pin_wkup_req_o))'
UVM_ERROR @ 2765.165500 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
UVM_INFO @ 2765.165500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98908) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 104223793722923967212300563882145428158449427203729089092459050499178926947966 416
UVM_ERROR @ 4485.957910 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98908) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4485.957910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 56629019844156879020350262913958228132487431978855226158676464180010419395251 413
UVM_ERROR @ 34964.350418 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34964.350418 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_hmac_oneshot 97616248362192332065885912675007892695957080152093502912303434952709227450342 415
UVM_ERROR @ 12026.705418 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
UVM_INFO @ 12026.705418 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:* = ErrorError
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 68778022367517927606325808550701258349146412114768984070962754241563149396250 404
UVM_ERROR @ 5361.935880 us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:0 = ErrorError
UVM_INFO @ 5361.935880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
chip_sw_all_escalation_resets 96611186215683286257384880139987397409283614124353543369832452643577476332010 398
UVM_ERROR @ 2882.667360 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 2882.667360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 57591738653509406036727959386743571285600053036324403645999691931571457866970 403
UVM_ERROR @ 3558.951528 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 3558.951528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---