clkmgr Simulation Results

Simulation Results: clkmgr

14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.41 %

code
98.95 %

assert
96.47 %

func
87.82 %

line
99.34 %

branch
99.17 %

cond
96.26 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		98.12%
V3		99.00%

130/130 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	clkmgr_smoke	2.070s	314.375us	50	50	100.00
csr_hw_reset				5	5	100.00
	clkmgr_csr_hw_reset	1.120s	47.780us	5	5	100.00
csr_rw				20	20	100.00
	clkmgr_csr_rw	1.160s	55.629us	20	20	100.00
csr_bit_bash				5	5	100.00
	clkmgr_csr_bit_bash	7.340s	1373.200us	5	5	100.00
csr_aliasing				5	5	100.00
	clkmgr_csr_aliasing	1.950s	399.880us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	clkmgr_csr_mem_rw_with_rand_reset	1.630s	50.085us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	clkmgr_csr_rw	1.160s	55.629us	20	20	100.00
	clkmgr_csr_aliasing	1.950s	399.880us	5	5	100.00

640/640 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				50	50	100.00
	clkmgr_peri	1.320s	105.016us	50	50	100.00
trans_enables				50	50	100.00
	clkmgr_trans	1.440s	73.951us	50	50	100.00
extclk				50	50	100.00
	clkmgr_extclk	1.320s	80.562us	50	50	100.00
clk_status				50	50	100.00
	clkmgr_clk_status	1.370s	149.964us	50	50	100.00
jitter				50	50	100.00
	clkmgr_smoke	2.070s	314.375us	50	50	100.00
frequency				50	50	100.00
	clkmgr_frequency	13.830s	2114.097us	50	50	100.00
frequency_timeout				50	50	100.00
	clkmgr_frequency_timeout	14.040s	2420.776us	50	50	100.00
frequency_overflow				50	50	100.00
	clkmgr_frequency	13.830s	2114.097us	50	50	100.00
stress_all				50	50	100.00
	clkmgr_stress_all	61.940s	12854.417us	50	50	100.00
alert_test				50	50	100.00
	clkmgr_alert_test	1.460s	235.174us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	clkmgr_tl_errors	3.910s	588.820us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	clkmgr_tl_errors	3.910s	588.820us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	clkmgr_csr_hw_reset	1.120s	47.780us	5	5	100.00
	clkmgr_csr_rw	1.160s	55.629us	20	20	100.00
	clkmgr_csr_aliasing	1.950s	399.880us	5	5	100.00
	clkmgr_same_csr_outstanding	2.130s	588.693us	20	20	100.00
tl_d_partial_access				50	50	100.00
	clkmgr_csr_hw_reset	1.120s	47.780us	5	5	100.00
	clkmgr_csr_rw	1.160s	55.629us	20	20	100.00
	clkmgr_csr_aliasing	1.950s	399.880us	5	5	100.00
	clkmgr_same_csr_outstanding	2.130s	588.693us	20	20	100.00

V2S

574/585 passed

98.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				22	25	88.00
	clkmgr_sec_cm	2.720s	489.253us	2	5	40.00
	clkmgr_tl_intg_err	2.770s	446.226us	20	20	100.00
shadow_reg_update_error				20	20	100.00
	clkmgr_shadow_reg_errors	3.650s	953.836us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	clkmgr_shadow_reg_errors	3.650s	953.836us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	clkmgr_shadow_reg_errors	3.650s	953.836us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	clkmgr_shadow_reg_errors	3.650s	953.836us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	clkmgr_shadow_reg_errors_with_csr_rw	5.480s	2264.317us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	clkmgr_tl_intg_err	2.770s	446.226us	20	20	100.00
sec_cm_meas_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency	13.830s	2114.097us	50	50	100.00
sec_cm_timeout_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency_timeout	14.040s	2420.776us	50	50	100.00
sec_cm_meas_config_shadow				20	20	100.00
	clkmgr_shadow_reg_errors	3.650s	953.836us	20	20	100.00
sec_cm_idle_intersig_mubi				50	50	100.00
	clkmgr_idle_intersig_mubi	2.000s	489.480us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				50	50	100.00
	clkmgr_lc_ctrl_intersig_mubi	1.460s	81.320us	50	50	100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi				50	50	100.00
	clkmgr_lc_clk_byp_req_intersig_mubi	1.320s	107.979us	50	50	100.00
sec_cm_clk_handshake_intersig_mubi				48	50	96.00
	clkmgr_clk_handshake_intersig_mubi	1.600s	109.341us	48	50	96.00
sec_cm_div_intersig_mubi				50	50	100.00
	clkmgr_div_intersig_mubi	1.730s	386.456us	50	50	100.00
sec_cm_jitter_config_mubi				20	20	100.00
	clkmgr_csr_rw	1.160s	55.629us	20	20	100.00
sec_cm_idle_ctr_redun				2	5	40.00
	clkmgr_sec_cm	2.720s	489.253us	2	5	40.00
sec_cm_meas_config_regwen				20	20	100.00
	clkmgr_csr_rw	1.160s	55.629us	20	20	100.00
sec_cm_clk_ctrl_config_regwen				20	20	100.00
	clkmgr_csr_rw	1.160s	55.629us	20	20	100.00
prim_count_check				2	5	40.00
	clkmgr_sec_cm	2.720s	489.253us	2	5	40.00

99/100 passed

99.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				50	50	100.00
	clkmgr_regwen	5.720s	975.973us	50	50	100.00
stress_all_with_rand_reset				49	50	98.00
	clkmgr_stress_all_with_rand_reset	69.910s	13687.638us	49	50	98.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
	clkmgr_sec_cm	56928346739215864967363154039105891672547246119658509580472566146477984682392	82	UVM_ERROR @ 23679655 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 23679655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	59164490300145567637526631606725113979144522149852179095506036154209454876140	80	UVM_ERROR @ 8884008 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 8884008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	182905537520968663774185487907720888662136636773594340653687700344517125212	74	UVM_ERROR @ 3959882 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 3959882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [] vs [*]) extclk_status mismatch
	clkmgr_clk_handshake_intersig_mubi	4941839966674363044655672965345559171115007285021137280892510587297154083207	71	UVM_ERROR @ 10112223 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (10 [0xa] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 10112223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_clk_handshake_intersig_mubi	71145339826156671280378980975653681413498040629328983549566220145053469659696	71	UVM_ERROR @ 68421239 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (13 [0xd] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 68421239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1142) [clkmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
	clkmgr_stress_all_with_rand_reset	102715509686447721128995706496239250885552105839629854356387556039920881363292	336	UVM_ERROR @ 14544871862 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. UVM_INFO @ 14544871862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---