Simulation Results: flash_ctrl

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.93 %
  • code
  • 95.87 %
  • assert
  • 96.62 %
  • func
  • 98.30 %
  • line
  • 96.11 %
  • branch
  • 97.49 %
  • cond
  • 94.96 %
  • toggle
  • 98.26 %
  • FSM
  • 92.52 %
Validation stages
V1
100.00%
V2
99.74%
V2S
99.88%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 125.940s 58.786us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 20.280s 50.022us 5 5 100.00
csr_hw_reset 5 5 100.00
flash_ctrl_csr_hw_reset 48.660s 106.850us 5 5 100.00
csr_rw 20 20 100.00
flash_ctrl_csr_rw 17.980s 38.702us 20 20 100.00
csr_bit_bash 5 5 100.00
flash_ctrl_csr_bit_bash 53.840s 6073.644us 5 5 100.00
csr_aliasing 5 5 100.00
flash_ctrl_csr_aliasing 62.860s 1596.526us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 17.140s 118.523us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
flash_ctrl_csr_rw 17.980s 38.702us 20 20 100.00
flash_ctrl_csr_aliasing 62.860s 1596.526us 5 5 100.00
mem_walk 5 5 100.00
flash_ctrl_mem_walk 9.740s 17.356us 5 5 100.00
mem_partial_access 5 5 100.00
flash_ctrl_mem_partial_access 13.540s 32.468us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 22.030s 27.995us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 103.220s 72.061us 5 5 100.00
rma_hw_if 43 43 100.00
flash_ctrl_hw_rma 1642.520s 212599.585us 3 3 100.00
flash_ctrl_hw_rma_reset 809.410s 160184.144us 20 20 100.00
flash_ctrl_lcmgr_intg 13.150s 41.680us 20 20 100.00
host_controller_arb 5 5 100.00
flash_ctrl_host_ctrl_arb 2002.600s 254044.272us 5 5 100.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 348.950s 12846.389us 5 5 100.00
program_reset 30 30 100.00
flash_ctrl_prog_reset 212.800s 5865.198us 30 30 100.00
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 3263.600s 135977.763us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 93.500s 2212.270us 5 5 100.00
rd_buff_eviction_w_ecc 98 100 98.00
flash_ctrl_rw_evict 31.760s 46.250us 38 40 95.00
flash_ctrl_rw_evict_all_en 32.170s 69.313us 40 40 100.00
flash_ctrl_re_evict 34.610s 89.099us 20 20 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 266.850s 185.741us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 266.850s 185.741us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 755.270s 29199.707us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 29.020s 1039.122us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 765.600s 188.738us 20 20 100.00
error_mp 10 10 100.00
flash_ctrl_error_mp 691.860s 27315.179us 10 10 100.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 647.040s 1665.151us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1309.730s 583.019us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 13.340s 97.888us 20 20 100.00
read_write_overflow 5 5 100.00
flash_ctrl_oversize_error 161.140s 16789.544us 5 5 100.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 22.480s 31.995us 50 50 100.00
flash_ctrl_connect 80 80 100.00
flash_ctrl_connect 16.860s 16.081us 80 80 100.00
stress_all 5 5 100.00
flash_ctrl_stress_all 601.530s 923.504us 5 5 100.00
secret_partition 130 130 100.00
flash_ctrl_hw_sec_otp 200.800s 13039.072us 50 50 100.00
flash_ctrl_otp_reset 134.370s 41.662us 80 80 100.00
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 1642.520s 212599.585us 3 3 100.00
interrupts 100 100 100.00
flash_ctrl_intr_rd 182.810s 6919.556us 40 40 100.00
flash_ctrl_intr_wr 91.050s 28331.668us 10 10 100.00
flash_ctrl_intr_rd_slow_flash 402.940s 49055.363us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 296.810s 72445.547us 10 10 100.00
invalid_op 20 20 100.00
flash_ctrl_invalid_op 76.590s 879.346us 20 20 100.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 67.120s 1845.547us 5 5 100.00
double_bit_err 35 35 100.00
flash_ctrl_read_word_sweep_derr 22.630s 75.568us 5 5 100.00
flash_ctrl_ro_derr 141.550s 2509.485us 10 10 100.00
flash_ctrl_rw_derr 237.880s 9947.767us 10 10 100.00
flash_ctrl_derr_detect 167.010s 9279.006us 5 5 100.00
flash_ctrl_integrity 515.110s 13790.479us 5 5 100.00
single_bit_err 25 25 100.00
flash_ctrl_read_word_sweep_serr 21.670s 25.699us 5 5 100.00
flash_ctrl_ro_serr 121.370s 1497.098us 10 10 100.00
flash_ctrl_rw_serr 204.260s 4533.114us 10 10 100.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 89.930s 5141.569us 5 5 100.00
singlebit_err_address 5 5 100.00
flash_ctrl_serr_address 86.010s 5895.803us 5 5 100.00
scramble 61 62 98.39
flash_ctrl_wo 207.000s 11231.675us 20 20 100.00
flash_ctrl_write_word_sweep 15.120s 40.226us 1 1 100.00
flash_ctrl_read_word_sweep 7.160s 33.523us 1 1 100.00
flash_ctrl_ro 107.550s 675.630us 20 20 100.00
flash_ctrl_rw 555.460s 10378.100us 19 20 95.00
filesystem_support 5 5 100.00
flash_ctrl_fs_sup 38.360s 497.945us 5 5 100.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 668.400s 53469.614us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 135.700s 10035.348us 20 20 100.00
alert_test 50 50 100.00
flash_ctrl_alert_test 15.360s 75.555us 50 50 100.00
intr_test 50 50 100.00
flash_ctrl_intr_test 13.570s 151.025us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
flash_ctrl_tl_errors 20.240s 65.997us 20 20 100.00
tl_d_illegal_access 20 20 100.00
flash_ctrl_tl_errors 20.240s 65.997us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
flash_ctrl_csr_hw_reset 48.660s 106.850us 5 5 100.00
flash_ctrl_csr_rw 17.980s 38.702us 20 20 100.00
flash_ctrl_csr_aliasing 62.860s 1596.526us 5 5 100.00
flash_ctrl_same_csr_outstanding 32.460s 262.176us 20 20 100.00
tl_d_partial_access 50 50 100.00
flash_ctrl_csr_hw_reset 48.660s 106.850us 5 5 100.00
flash_ctrl_csr_rw 17.980s 38.702us 20 20 100.00
flash_ctrl_csr_aliasing 62.860s 1596.526us 5 5 100.00
flash_ctrl_same_csr_outstanding 32.460s 262.176us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
flash_ctrl_shadow_reg_errors 100.760s 91.802us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
flash_ctrl_shadow_reg_errors 100.760s 91.802us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
flash_ctrl_shadow_reg_errors 100.760s 91.802us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
flash_ctrl_shadow_reg_errors 100.760s 91.802us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 73.370s 634.941us 20 20 100.00
tl_intg_err 25 25 100.00
flash_ctrl_tl_intg_err 770.210s 13957.427us 20 20 100.00
flash_ctrl_sec_cm 2116.270s 8137.511us 5 5 100.00
sec_cm_reg_bus_integrity 20 20 100.00
flash_ctrl_tl_intg_err 770.210s 13957.427us 20 20 100.00
sec_cm_host_bus_integrity 20 20 100.00
flash_ctrl_tl_intg_err 770.210s 13957.427us 20 20 100.00
sec_cm_mem_bus_integrity 6 6 100.00
flash_ctrl_rd_intg 26.470s 114.194us 3 3 100.00
flash_ctrl_wr_intg 15.210s 52.917us 3 3 100.00
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 125.940s 58.786us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 260 260 100.00
flash_ctrl_otp_reset 134.370s 41.662us 80 80 100.00
flash_ctrl_disable 22.480s 31.995us 50 50 100.00
flash_ctrl_sec_info_access 73.650s 5621.140us 50 50 100.00
flash_ctrl_connect 16.860s 16.081us 80 80 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 11.430s 70.084us 5 5 100.00
sec_cm_data_regions_config_regwen 20 20 100.00
flash_ctrl_csr_rw 17.980s 38.702us 20 20 100.00
sec_cm_data_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 100.760s 91.802us 20 20 100.00
sec_cm_info_regions_config_regwen 20 20 100.00
flash_ctrl_csr_rw 17.980s 38.702us 20 20 100.00
sec_cm_info_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 100.760s 91.802us 20 20 100.00
sec_cm_bank_config_regwen 20 20 100.00
flash_ctrl_csr_rw 17.980s 38.702us 20 20 100.00
sec_cm_bank_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 100.760s 91.802us 20 20 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 22.480s 31.995us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 26.470s 114.194us 3 3 100.00
flash_ctrl_access_after_disable 13.700s 172.733us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 30.740s 199.126us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 22.480s 31.995us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 29.020s 1039.122us 10 10 100.00
sec_cm_mem_scramble 19 20 95.00
flash_ctrl_rw 555.460s 10378.100us 19 20 95.00
sec_cm_mem_integrity 25 25 100.00
flash_ctrl_rw_serr 204.260s 4533.114us 10 10 100.00
flash_ctrl_rw_derr 237.880s 9947.767us 10 10 100.00
flash_ctrl_integrity 515.110s 13790.479us 5 5 100.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 1642.520s 212599.585us 3 3 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2116.270s 8137.511us 5 5 100.00
sec_cm_phy_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2116.270s 8137.511us 5 5 100.00
sec_cm_phy_prog_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2116.270s 8137.511us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2116.270s 8137.511us 5 5 100.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 16.590s 755.077us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 5 5 100.00
flash_ctrl_phy_host_grant_err 12.410s 74.341us 5 5 100.00
sec_cm_phy_ack_ctrl_consistency 5 5 100.00
flash_ctrl_phy_ack_consistency 12.780s 40.104us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2116.270s 8137.511us 5 5 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2116.270s 8137.511us 5 5 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2116.270s 8137.511us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 32.520s 98.572us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 282.700s 510.793us 3 3 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: *
flash_ctrl_rw_evict 21825130884201413020347416760057629137997825993170897961493949157985655354431 105
UVM_ERROR @ 11886.6 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 11886.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict 87754371008190285175345569817085383025132292746237152790345374795879154237145 105
UVM_ERROR @ 121263.7 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 121263.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
flash_ctrl_rw 97731903277746329407512396001841254288977483425516852865406146150056879902011 None
Job timed out after 60 minutes