Simulation Results: hmac

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.98 %
  • code
  • 99.32 %
  • assert
  • 97.61 %
  • func
  • 100.00 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.80 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 15.310s 4159.890us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.290s 73.024us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.080s 83.949us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 7.640s 718.289us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 4.820s 368.793us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 471.410s 178911.765us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.080s 83.949us 20 20 100.00
hmac_csr_aliasing 4.820s 368.793us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 52.450s 15078.916us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 97.340s 1547.070us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 287.140s 7313.889us 30 30 100.00
hmac_test_sha384_vectors 523.240s 12009.297us 75 75 100.00
hmac_test_sha512_vectors 516.670s 53917.074us 75 75 100.00
hmac_test_hmac256_vectors 14.150s 298.580us 50 50 100.00
hmac_test_hmac384_vectors 16.920s 1581.875us 60 60 100.00
hmac_test_hmac512_vectors 18.010s 823.850us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 36.220s 10284.767us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1365.280s 7381.119us 10 10 100.00
error 10 10 100.00
hmac_error 107.790s 57990.269us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 95.260s 3871.613us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 15.310s 4159.890us 10 10 100.00
hmac_long_msg 52.450s 15078.916us 10 10 100.00
hmac_back_pressure 97.340s 1547.070us 25 25 100.00
hmac_datapath_stress 1365.280s 7381.119us 10 10 100.00
hmac_burst_wr 36.220s 10284.767us 50 50 100.00
hmac_stress_all 2208.750s 69970.428us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 15.310s 4159.890us 10 10 100.00
hmac_long_msg 52.450s 15078.916us 10 10 100.00
hmac_back_pressure 97.340s 1547.070us 25 25 100.00
hmac_datapath_stress 1365.280s 7381.119us 10 10 100.00
hmac_wipe_secret 95.260s 3871.613us 10 10 100.00
hmac_test_sha256_vectors 287.140s 7313.889us 30 30 100.00
hmac_test_sha384_vectors 523.240s 12009.297us 75 75 100.00
hmac_test_sha512_vectors 516.670s 53917.074us 75 75 100.00
hmac_test_hmac256_vectors 14.150s 298.580us 50 50 100.00
hmac_test_hmac384_vectors 16.920s 1581.875us 60 60 100.00
hmac_test_hmac512_vectors 18.010s 823.850us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 15.310s 4159.890us 10 10 100.00
hmac_long_msg 52.450s 15078.916us 10 10 100.00
hmac_back_pressure 97.340s 1547.070us 25 25 100.00
hmac_datapath_stress 1365.280s 7381.119us 10 10 100.00
hmac_burst_wr 36.220s 10284.767us 50 50 100.00
hmac_error 107.790s 57990.269us 10 10 100.00
hmac_wipe_secret 95.260s 3871.613us 10 10 100.00
hmac_test_sha256_vectors 287.140s 7313.889us 30 30 100.00
hmac_test_sha384_vectors 523.240s 12009.297us 75 75 100.00
hmac_test_sha512_vectors 516.670s 53917.074us 75 75 100.00
hmac_test_hmac256_vectors 14.150s 298.580us 50 50 100.00
hmac_test_hmac384_vectors 16.920s 1581.875us 60 60 100.00
hmac_test_hmac512_vectors 18.010s 823.850us 75 75 100.00
hmac_stress_all 2208.750s 69970.428us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2208.750s 69970.428us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.930s 42.654us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.860s 17.755us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 3.360s 205.995us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 3.360s 205.995us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.290s 73.024us 5 5 100.00
hmac_csr_rw 1.080s 83.949us 20 20 100.00
hmac_csr_aliasing 4.820s 368.793us 5 5 100.00
hmac_same_csr_outstanding 2.030s 501.912us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.290s 73.024us 5 5 100.00
hmac_csr_rw 1.080s 83.949us 20 20 100.00
hmac_csr_aliasing 4.820s 368.793us 5 5 100.00
hmac_same_csr_outstanding 2.030s 501.912us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_tl_intg_err 3.480s 282.030us 20 20 100.00
hmac_sec_cm 1.410s 177.927us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 3.480s 282.030us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 15.310s 4159.890us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.540s 340.085us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 493.900s 82995.754us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.080s 59.452us 1 1 100.00

Error Messages

   Test seed line log context